Technical Library | 2023-01-17 17:22:28.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC- 9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2023-01-17 17:12:33.0
Reflowed indium metal has for decades been the standard for solder thermal interface materials (solder TIMs or sTIMs) in most high-performance computing (HPC) TIM1 applications. The IEEE Heterogeneous Integration Thermal roadmap states that new thermal interface materials solutions must provide a path to the successful application of increased total-package die areas up to 100cm2. While GPU architectures are relatively isothermal during usage, CPU hotspots in complex heterogeneously-integrated modules will need to be able to handle heat flux hotspots up to 1000W/cm2 within the next two years. Indium and its alloys are used as reflowed solder thermal interface materials in both CPU and GPU "die to lid/heat spreader" (TIM1) applications. Their high bulk thermal conductivity and proven long-term reliability suit them well for extreme thermomechanical stresses. Voiding is the most important failure mode and has been studied by x-ray. The effects of surface pretreatment, pressure during reflow, solder flux type/fluxless processing, and preform design parameters, such as alloy type, are also examined. The paper includes data on both vacuum and pressure (autoclave) reflow of sTIMs, which is becoming necessary to meet upcoming requirements for ultralow voiding in some instances.
Technical Library | 2023-09-07 14:54:10.0
A global manufacturer of a broad line of electronic interconnect solutions worked with us to dispense conductive adhesive EpoTek H20E-FC. EpoTek H20E-FC is a two-component, electrically conductive, snap curing epoxy for photovoltaic thin film module stringing, semiconductor packaging and PCB circuit assembly. The primary goal was filling a rectangular cavity on a connector. The epoxy needed to fill the connector to the top of the walls in less than three seconds.
Technical Library | 2019-06-05 11:11:06.0
As electronic products increase in functionality and complexity, there is an emphasis on affordability, miniaturization, and energy efficiency. The telecommunications, automotive, and commercial electronic markets are the leading drivers for these trends. These markets see high volume manufacturing with millions of units priced to the fraction of the cent. The choice of the packaging material for the electrical components for these markets can have a substantial effect on the cost of the final product. Therefore plastic encapsulated components are almost universally used in non-military applications over the conventional ceramic or metal electronic packages.
Technical Library | 2021-06-15 15:17:33.0
Shielding electronic systems against electromagnetic interference (EMI) has become a hot topic. Technological advancements toward 5G standards, wireless charging of mobile electronics, in-package antenna integration, and system-in-package (SiP) adoption are driving the need to apply more effective EMI shielding and isolation to component packages and larger modules. For conformal shielding, EMI shielding materials for exterior package surfaces have mostly been applied with a physical vapor deposition (PVD) process of sputtering, leveraging front-end packaging technologies to back-end packaging applications. However, sputtering technology challenges in scalability and cost along with advancements in dispensable materials are driving considerations for alternative dispensing techniques for EMI shielding.
Technical Library | 2020-02-26 23:24:02.0
Shielding electronic systems against electromagnetic interference (EMI) has become a hot topic. Technological advancements toward 5G standards, wireless charging of mobile electronics, in-package antenna integration, and system-inpackage (SiP) adoption are driving the need to apply more effective EMI shielding and isolation to component packages and larger modules. For conformal shielding, EMI shielding materials for exterior package surfaces have mostly been applied with a physical vapor deposition (PVD) process of sputtering, leveraging front-end packaging technologies to back-end packaging applications. However, sputtering technology challenges in scalability and cost along with advancements in dispensable materials are driving considerations for alternative dispensing techniques for EMI shielding.
Technical Library | 2020-08-05 17:13:12.0
A primary issue in electronics reliability for military applications is the ability to ensure long term operability in harsh, extreme environments. This requires more rigid standards, such as the MIL-STD-883 (Department of Defense Test Method Standard for Microcircuits), which commercial grade electronics typically do not satisfy. A solution commonly employed is to package the critical electronic components in hermetically sealed metal or ceramic enclosures which are costly and labor intensive. Not only are the components more expensive, but the assembly process is more difficult to automate, resulting in a substantial cost premium for military grade electronics.
Technical Library | 2019-10-16 10:20:25.0
A major goal of the development of advanced packaging technology is to reduce the size, weight, and power consumption of electronics components using state-of-the-art commercial technologies. One of the novel concepts involves the use of all three spatial dimensions when designing and producing new systems. In the past, electronic structures tended to be two dimensional in nature. Generally speaking, individually packaged integrated circuit (IC) dies were interconnected on printed circuit boards. Techniques such as die and package stacking naturally contribute to a reduction of the spatial footprint of any given electronic system design.
Technical Library | 2019-06-06 13:40:47.0
Legacy electronics assemblies, such as through-hole (Figure 1) and connectorized component packages, are robust and prevalent throughout industry. However, each of these assembly methods have reached their limits in terms of weight, volume, reliability, and most importantly cost. With cost reduction of assemblies now the primary focus area throughout the electronics industry, there is more of a need than ever to implement the latest advancements in surface mount technology (SMT) into electronics assembly designs. Although SMT has been utilized in the electronics industry for many years, implementation of the technology is still in the ever-evolving process of reducing component footprint size, component spacing, and component I/O pitch. Implementation of the most up-to-date SMT processes provides optimal weight, volume, and cost savings, for any type of assembly.
Technical Library | 2019-05-24 09:27:33.0
Decapsulation, or de-cap, is a failure analysis technique which involves the removal of material packaging from an integrated circuit (IC). After de-cap, visual inspection by optical microscopy of the internal circuitry may reveal areas where damage is most likely to have occurred. In addition, scanning electron microscopy (SEM) with energy dispersive x-ray spectroscopy (EDS) can identify the composition of any anomalies present after de-cap under higher magnification. The removal process of package material can be done either mechanically or chemically depending on the design of the integrated circuit. With ceramic packaging, de-cap is usually done mechanically by chiseling off the top with a fine razor and small hammer. For plastic packaging, de-cap requires chemical etching by strong acids. In this Tech Tips article, de-cap by chemical etching will be outlined step by step.
Manufacturer of PCB depaneling and PCB soldering machines since 2005, products include CE approval V-groove PCB depanelizer, PCB router, PCB punching machine, laser depaneling, hot bar soldering machines and soldering robots.
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Huizhou, 30 China
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