Technical Library: electronic packages (Page 6 of 13)

Miniaturization with Help of Reduced Component to Component Spacing

Technical Library | 2015-03-12 18:26:16.0

Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the active and passive components. There are many ways to increase the packaging density and a few examples would be to stack them with Package on Package (PoP), fine pitch CSP's, 01005 and last but not least reduced component to component spacing for active and passive components (...)This paper will discuss different layouts, assembly and material selections to reduce component to component spacing down to 100-125um (4-5mil) from today’s mainstream of 150-200um (6-8mil) component to component spacing.

Flex (Flextronics International)

Process Development And Characterization Of The Stencil Printing Process For Small Apertures

Technical Library | 2008-01-16 18:25:55.0

The consumer's interest for smaller, lighter and higher performance electronics products has increased the use of ultra fine pitch packages, such as Flip Chips and Chip Scale Packages, in printed circuit board (PCB) assembly. The assembly processes for these ultra fine pitch packages are extremely complex and each step in the assembly process influences the assembly yield and reliability.

Speedline Technologies, Inc.

A Novel High Thermal Conductive Underfill For Flip Chip Appliation

Technical Library | 2014-02-27 15:30:20.0

Silicon dioxide is normally used as filler in underfill. The thermal conductivity of underfill is less than 1 w/mk, which is not able to meet the current flip chip application requirements such as 3D stacked multi-chips packaging. No matter which direction the heat will be dissipated through PCB or chip, the heat has to pass through the underfill in 3D stacked chips. Therefore the increase of thermal conductivity of underfill can significantly enhance the reliability of electronic devices, particularly in 3D package devices

YINCAE Advanced Materials, LLC.

Stress Analysis and Optimization of a Flip Chip on Flex Electronic Packaging Method for Functional Electronic Textiles

Technical Library | 2020-12-24 02:50:56.0

A method for packaging integrated circuit silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm×8 mm× 0.53 mm and 2 mm×2 mm×0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three underfill adhesives (EP30AO, EP37-3FLF, and Epo-Tek 301 2fl), three highly flexible adhesives (Loctite 4860, Loctite 480, and Loctite 4902), and three substrates (Kapton,Mylar, and PEEK) have been evaluated, and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, was identified as the best materials combination with the optimum underfill and substrate thickness identified as 0.05 mm.

University of Southampton

Influence of Flexibility of the Interconnects on the Dynamic Bending Reliability of Flexible Hybrid Electronics

Technical Library | 2021-08-18 01:27:15.0

The growing interest towards thinner and conformable electronic systems has attracted significant attention towards flexible hybrid electronics (FHE). Thin chip-foil packages fabricated by integrating ultra-thin monocrystalline silicon integrated circuits (ICs) on/in flexible foils have the potential to deliver high performance electrical functionalities at very low power requirements while being mechanically flexible.

Fraunhofer EMFT Research Institution for Microsystems and Solid State Technologies

Soft, Wireless Periocular Wearable Electronics For Real-Time Detection Of Eye Vergence In A Virtual Reality Toward Mobile Eye Therapies

Technical Library | 2020-07-22 19:24:33.0

Recent advancements in electronic packaging and image processing techniques have opened the possibility for optics-based portable eye tracking approaches, but technical and safety hurdles limit safe implementation toward wearable applications. Here, we introduce a fully wearable, wireless soft electronic system that offers a portable, highly sensitive tracking of eye movements (vergence) via the combination of skin-conformal sensors and a virtual reality system. Advancement of material processing and printing technologies based on aerosol jet printing enables reliable manufacturing of skin-like sensors, while the flexible hybrid circuit based on elastomer and chip integration allows comfortable integration with a user's head. Analytical and computational study of a data classification algorithm provides a highly accurate tool for real-time detection and classification of ocular motions. In vivo demonstration with 14 human subjects captures the potential of the wearable electronics as a portable therapy system, whose minimized form factor facilitates seamless interplay with traditional wearable hardware.

Georgia Institute of Technology

The Reliability Challenges of QFN Packaging

Technical Library | 2010-05-27 22:12:10.0

The quad flat pack no lead or quad flat non-leaded (QFN) is one of the fastest growing package types in the electronics industry today. While the advantages of QFNs are well documented, concerns arise with its reliability and manufacturability. Acceptance of this package, especially in long-life, severe-environment, high-reliability applications, is currently limited. One of the most common drivers for reliability failures is inappropriate adoption of new technologies, such as the case with QFN. In this presentation, we will review and discuss QFN related reliability concerns and challenges, and propose Physics-of-Failure (PoF) based approaches to allow the confident introduction of QFN components into electronics products.

DfR Solutions

Low Melting Temperature Sn-Bi Solder: Effect of Alloying and Nanoparticle Addition on the Microstructural, Thermal, Interfacial Bonding, and Mechanical Characteristics

Technical Library | 2021-05-13 16:03:25.0

Sn-based lead-free solders such as Sn-Ag-Cu, Sn-Cu, and Sn-Bi have been used extensively for a long time in the electronic packaging field. Recently, low-temperature Sn-Bi solder alloys attract much attention from industries for flexible printed circuit board (FPCB) applications. Low melting temperatures of Sn-Bi solders avoid warpage wherein printed circuit board and electronic parts deform or deviate from the initial state due to their thermal mismatch during soldering. However, the addition of alloying elements and nanoparticles Sn-Bi solders improves the melting temperature, wettability, microstructure, and mechanical properties. Improving the brittleness of the eutecticSn-58wt%Bi solder alloy by grain refinement of the Bi-phase becomes a hot topic. In this paper, literature studies about melting temperature, microstructure, inter-metallic thickness, and mechanical properties of Sn-Bi solder alloys upon alloying and nanoparticle addition are reviewed

University of Seoul

Evaluating the Mechanical Reliability of Ball Grid Array (BGA) Flexible Surface-Mount Electronics Packaging under Isothermal Ageing

Technical Library | 2015-02-12 16:57:56.0

Electronic systems are known to be affected by the environmental and mechanical conditions, such as humidity, temperature, thermal shocks and vibration. These adverse environmental operating conditions, with time, could degrade the mechanical efficiency of the system and might lead to catastrophic failures.The aim of this study is to investigate the mechanical integrity of lead-free ball grid array (BGA) solder joints subjected to isothermal ageing at 150°C for up to 1000 hours. Upon ageing at 150°C the Sn-3.5Ag solder alloy initially age-softened for up to 200 hours. This behaviour was linked to the coarsening of grains. When aged beyond 200 hours the shear strength was found to increase up to 400 hours. This age-hardening was correlated with precipitation of hard Ag3Sn particles in Sn matrix. Further ageing resulted in gradual decrease in shear strength. This can be explained as the combined effect of precipitation coarsening and growth of intermetallic layer. The fractured surfaces of the broken solder balls were also investigated under a Scanning Electron Microscope. The shear failures were generally due to ductile fractures in bulk solders irrespective of the ageing time.

School of Engineering, University of Greenwich

Process Issues For Fine Pitch CSP Rework and Scavenging

Technical Library | 2013-03-04 16:51:00.0

Chip-scale (or chip-size) packages are rapidly becoming an important element in electronics due to their size, performance, and cost advantages [Hou, 1998]. The Chip Scale Package (CSP) is becoming a key semiconductor package type, particularly for consumer products. Due to their relatively smaller size, new challenges are presented in the rework and repair of CSPs. (...) The specific focus of this paper is the removal process for rework of CSPs and the site scavenging methods required to properly prepare the circuit board for a new component. Process factors such as the heating, fluxing and, atmosphere are discussed.

Universal Instruments Corporation


electronic packages searches for Companies, Equipment, Machines, Suppliers & Information

Winsmart Electronic Co.,Ltd
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Manufacturer of PCB depaneling and PCB soldering machines since 2005, products include CE approval V-groove PCB depanelizer, PCB router, PCB punching machine, laser depaneling, hot bar soldering machines and soldering robots.

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