Technical Library | 2019-01-20 22:47:35.0
With the rapid development of the electronics industry, more and more components such as integrated circuits and connectors, relays, power modules, etc. need to be packaged with IC tubes. The anti static ic tubes is actually a kind of pvc plastic(reference to : What are the materials for IC tubes) profile, the size varies with the shape of the installed product, the precision requirement is high, the wall thickness should be controlled within ±0.1mm, and the surface is required to have no impurity spots, smooth and transparent. The IC packaging tubes produced by Sewate Technology Co., Ltd. are extruded. The typical process flow is: extrusion, vacuum adsorption setting, traction, fixed length cutting and directional discharge, deburring, immersion antistatic liquid, drying, testing, packaging and storage
Technical Library | 2003-05-05 07:36:58.0
The stencil selection process can be confusing, particularly when creating a stencil for a new application. This tutorial, which covers stencils for SMT and advanced IC packaging applications, offers guidelines to assist users in stencil selection and print optimization.
Technical Library | 2007-10-02 22:09:50.0
The vast majority (99%) of the electronics market in North America is composed of products produced for commercial applications. The 1% share of the electronics market driven by Department of Defense (DoD) applications has created a niche market for RF qualified devices. The DoD, with its emphasis on COTS (Commercial Off The Shelf) and "Open" systems, is beginning to become more interested in using commercially oriented RF devices for military applications as a means to leverage the volumes and innovations of the commercial world.
Technical Library | 2015-03-04 10:56:26.0
As the proliferation of modern day electronics continues to drive miniaturization and functionality, electronic designers/assemblers face the issue of environmental exposure and uncommon applications never previously contemplated. This reality, coupled with the goal of reducing the environmental and health implications of the production and disposal of these devices, has forced manufacturers to reconsider the materials used in production. Furthermore, the need to increase package density and reduce costs has led to the rapid deployment of leadless packages such as QFN, POP, LGA, and Micro-BGA. In many cases, the manufacturers of these devices will recommend the use of no clean fluxes due to concerns over the ability to consistently remove flux residues from under and around these devices. These concerns, along with the need to implement a tin whisker mitigation strategy and/or increase environmental tolerance, have led to the conundrum of applying conformal coating over no clean residues.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2020-01-01 17:06:52.0
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.
Technical Library | 2009-02-26 03:25:09.0
STI has developed a patented1 packaging technology coined Imbedded Component/Die Technology (IC/DT®) to integrate multiple subsystems within an electronics assembly into a single, advanced, high-density assembly. Imbedded Component/Die Technology (IC/DT®) enables the manufacturing and assembly of smaller, lighter, and more technologically advanced high density CCAs through imbedding unpackaged components in a 3-D laminate substrate with integrated thermal management
Technical Library | 2015-04-08 11:10:47.0
An electronic schematic describes the electrical connectivity of a piece of equipment or an entire system. It is made up of symbols that represent individual components and contains electrical and mechanical information and their related connectivity, along with other important data. Information contained within the schematic is packaged into a printed circuit board (PCB) where the mechanical footprint is placed onto the board and connectivity information is graphically displayed. The more accurate the information contained in the schematic is and the clearer it is presented, the more it contributes to a robust printed circuit board.
Technical Library | 2015-05-11 21:27:52.0
Originating from the last millenium, almost three decades ago, the introduction of surface mount packaging triggered a wave of changes throughout many aspects of electronics production. A small number of talented, innovative test engineers from various big players of the industry started to attend meetings to discuss the impact of that change of technology on their future test concepts for modern assemblies. The Joint Test Action Group was born.
Technical Library | 2023-06-12 16:52:47.0
The technological advancement of component and PCB technology from through-hole to surface mount (SMT) is a major factor in the miniaturization of today's electronics. Smaller and smaller component sizes and more densely packed PCBs lead to more powerful designs in much smaller product packages. With advancement, however, comes a new set of challenges in building these smaller, more complex assemblies. This is the challenge original equipment manufacturers (OEM) and contract manufacturers (CM) face today.
Manufacturer of PCB depaneling and PCB soldering machines since 2005, products include CE approval V-groove PCB depanelizer, PCB router, PCB punching machine, laser depaneling, hot bar soldering machines and soldering robots.
Liwu Industrial Park, Yuanzhou Town, Boluo
Huizhou, 30 China
Phone: +86-138-29839112
