Technical Library | 2008-03-03 19:43:53.0
Solder pastes are key materials in surface mount technology (SMT) for assembly of printed circuit boards (PCBs). Introduction of lead-free has placed new demands on materials and processes in SMT, requiring materials and process engineers to adopt to lead free whilst ensuring process yields stay at the highest possible levels. Key is the solder paste, a material of great complexity involving engineering sciences, metallurgy, chemistry and physics. This article helps those working with solder pastes improve their understanding of this key material.
Technical Library | 1999-04-15 08:21:22.0
Intel's Packaging Databook is intended to serve as a data reference for engineering design, as well as a guide to Intel package selection and availability. IC assembly, performance characteristics, physical constants, detailed discussions of SMT, etc.
Technical Library | 2013-12-11 23:24:32.0
Today's analyses of electronics reliability at the system level typically use a "black box approach", with relatively poor understanding of the behaviors and performances of such "black boxes" and how they physically and electrically interact (...) The incorporation of more rigorous and more informative approaches and techniques needs to better understand (...) Understanding the Physics of Failure (PoF) is imperative. It is a formalized and structured approach to Failure Analysis/Forensics Engineering that focuses on total learning and not only fixing a particular current problem (...) In this paper we will present an explanation of various physical models that could be deployed through this method, namely, wire bond failures; thermo-mechanical fatigue; and vibration.
Technical Library | 2019-11-17 22:46:45.0
Overview of walk-in temperature and humidity chamber: It also belongs to environmental test equipment, it tests whether the product can resist high temperature, low temperature, humidity, or the physical and chemical changes produced under extreme conditions, the walk-in temperature and humidity chamber volume is large, the product is placed, or a large object can be placed, such as automobile, new energy, television and liquid crystal screen, etc. How to do the routine maintenance of the walk-in temperature and humidity chamber: 1. The wet gauze basically, if there is no special case, s/b usually changed once in 3 months 2. The water channel shall be regularly cleaned, including water cup, water tank, etc., so as to prevent the water from being blocked,affect the humidity test. 3. It is forbidden to test the flammable and explosive products inside working room. 4. Clean the chamber on a regular basis 2. How to operate walk-in temperature and humidity chamber: The operation method is same as standard temperature humidity test chamber,the controller is 7-inch LCD programmable color screen, you only need to setthe temperature point---test time--how many cycles need to be tested, This can be done automatically, and the machine will stop automatically when it is complete. If there is any problem during the operation, the corresponding problem point will be displayed on the machine control screen. Walk-in temperature and humidity chamber is a must equipment for reliability test of Automobile,Aerospace,Electronic parts,etc,the operation and maintenance are easy,it is teh tear down mahcine,Climatest engineers will be dispatched to do on-site support,for instance,we will finish commissioning,train customers how to operate,maintain,welcome to follow our company facebook page:https://www.facebook.com/Climatechambers
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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