Technical Library: feature (Page 3 of 6)

An Automatic Optical Inspection System for the Diagnosis of Printed Circuits Based on Neural Networks

Technical Library | 2021-11-22 20:32:10.0

The aim of this work is to define a procedure to develop diagnostic systems for Printed Circuit Boards, based on Automated Optical Inspection with low cost and easy adaptability to different features. A complete system to detect mounting defects in the circuits is presented in this paper. A low cost image acquisition system with high accuracy has been designed to fit this application. Afterward, the resulting images are processed using the Wavelet Transform and Neural Networks, for low computational cost and acceptable precision. The wavelet space represents a compact support for efficient feature extraction with the localization property. The proposed solution is demonstrated on several defects in different kind of circuits.

Vienna University of Technology [TU Wien]

21st Century Semiconductor Manufacturing Capabilities

Technical Library | 1999-05-06 14:44:11.0

Semiconductor device manufacturers face many difficult challenges as we enter the 21st century. Some are direct consequences of adherence to Gordon Moore's Law, which states that device complexity doubles about every 18 months. Feature size reduction, increased wafer diameter, increased chip size, ultra-clean processing, and defect reduction among others are manifestations that have a direct bearing on the cost and quality of products, factory flexibility in responding to changing technology or business conditions, and on the timelines of product delivery to the ultimate customer.

Intel Corporation

Evaluating Automated Wafer Measurement Instruments

Technical Library | 1999-08-05 09:34:44.0

This document demonstrates a sequential process of evaluating automated wafer instruments and discusses why this approach is useful for studying instruments that have automation features such as loading and focusing mechanisms. The methodology specifies a series of experiments consisting of two or more capability studies followed by a stability study. Each experiment achieves a separate goal, yet combines with the others in providing information needed to assess the usefulness of the instrument.

SEMATECH

Cree® XLamp® LED Thermal Management

Technical Library | 2009-06-11 18:28:24.0

XLamp LEDs lead the solid-state lighting industry in brightness while providing a reflow-solderable design that is optimized for ease of use and thermal management. Lighting applications featuring XLamp LEDs maximize light output and increase design flexibility, while minimizing environmental impact. This application note serves as a guide to understanding thermal management of XLamp LEDs and minimizing the effects of elevated junction temperatures.

Cree, Inc.

Joule Heating Effects on the Current Carrying Capacity of an Organic Substrate for Flip-Chip Applications

Technical Library | 2009-07-22 18:33:41.0

This paper deals with the thermal effects of joule heating in a high interconnect density, thin core, buildup, organic flip chip substrate. The 440 μm thick substrate consists of a 135 μm thick core with via density of about 200 μm. The typical feature sizes in the substrate are 50 micron diameter vias is the core/buildup layers and 12 micron thick metal planes. An experimental test vehicle is powered with current and the temperature rise was measured. A numerical model was used to simulate the temperature rise in the TV.

i3 Electronics

Characterization, Prevention and Removal of Particulate Matter on Printed Circuit Boards

Technical Library | 2016-12-22 16:44:04.0

Particulate matter contamination is known to become wet and therefore ionically conductive and corrosive if the humidity in the environment rises above the deliquescence relative humidity (DRH) of the particulate matter. In wet condition, particulate matter can electrically bridge closely spaced features on printed circuit boards (PCBs), leading to their electrical failure. (...) The objective of this paper is to develop and describe a practical, routine means of measuring the DRH of minute quantities of particulate matter (1 mg or less) found on PCBs.

IBM Corporation

Additively Manufactured mm-Wave Multichip Modules With Fully Printed "Smart" Encapsulation Structures

Technical Library | 2022-02-09 17:52:47.0

This article presents the first time that an millimeter-wave (mm-wave) multichip module (MCM) with on-demand "smart" encapsulation has been fabricated utilizing additive manufacturing technologies. RF and dc interconnects were fabricated using inkjet printing, while the encapsulation was realized using 3-D printing. Inkjet-printed interconnects feature superior RF performance, better mechanical reliability, and on-demand, low-cost fabrication process.

Georgia Institute of Technology

LEAD-FREE FLUX TECHNOLOGY AND INFLUENCE ON CLEANING

Technical Library | 2022-10-11 17:27:08.0

Lead-free flux technology for electronic industry is mainly driven by high soldering temperature, high alloy surface tension, miniaturization, air soldering due to low cost consideration, and environmental concern. Accordingly, the flux features desired included high thermal stability, high resistance against burn-off, high oxidation resistance, high oxygen barrier capability, low surface tension, high fluxing capacity, slow wetting, low moisture pickup, high hot viscosity, and halogen-free. For each of the features listed above, corresponding desired chemical structures can be deduced, and the impact of those structures on flux residue cleanability can be speculated. Overall, lead-free flux technology results in a greater difficulty in cleaning. Cleaner with a better matching solvency for the residue as well as a higher cleaning temperature or agitation are needed. Alkaline and polar cleaner are often needed to deal with the larger quantity of fluxing products. Reactive cleaner is also desired to address the side reaction products such as crosslinked residue.

Indium Corporation

New High-Speed 3D Surface Imaging Technology in Electronics Manufacturing Applications

Technical Library | 2020-03-26 14:55:29.0

This paper introduces line confocal technology that was recently developed to characterize 3D features of various surface and material types at sub-micron resolution. It enables automatic microtopographic 3D imaging of challenging objects that are difficult or impossible to scan with traditional methods, such as machine vision or laser triangulation.Examples of well-suited applications for line confocal technology include glossy, mirror-like, transparent and multi-layered surfaces made of metals (connector pins, conductor traces, solder bumps etc.), polymers (adhesives, enclosures, coatings, etc.), ceramics (components, substrates, etc.) and glass (display panels, etc.). Line confocal sensors operate at high speed and can be used to scan fast-moving surfaces in real-time as well as stationary product samples in the laboratory. The operational principle of the line confocal method and its strengths and limitations are discussed.Three metrology applications for the technology in electronics product manufacturing are examined: 1. 3D imaging of etched PCBs for micro-etched copper surface roughness and cross-sectional profile and width of etched traces/pads. 2. Thickness, width and surface roughness measurement of conductive ink features and substrates in printed electronics applications. 3. 3D imaging of adhesive dots and lines for shape, dimensions and volume in PCB and product assembly applications.

FocalSpec, Inc.

PTH Core-to-Core Interconnect Using Sintered Conductive Pastes

Technical Library | 2013-03-07 18:25:36.0

The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings

Ormet Circuits, Inc.


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