Technical Library | 2020-07-15 18:49:03.0
Via Filling • Through Hole Vias - IPC-4761 – Plugging – Filling – Filled & Capped • MicroviaFilling and Stacked Vias
Technical Library | 2008-08-28 22:50:11.0
The increasing use of lead-free solder has introduced a new set of process parameters when setting up wave solder equipment for effective soldering. Determining the proper flow characteristics of the solder wave for adequate hole fill is an essential step in achieving a reliable process. A variety of solder waves exist in the industry; each with advantages and disadvantages when performing lead-free wave soldering. One way to ensure adequate hole-fill is by increasing contact time at the Chip Wave.
Technical Library | 2020-03-12 13:10:35.0
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs.
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2023-11-14 19:52:11.0
The continuous drive in the Electronics industry to build new and innovative products has caused competitive design companies to develop assemblies with consolidated PCB designs, decreased physical sizes, and increased performance characteristics. As a result of these new designs, manufacturers of electronics are forced to contend with many challenges. One of the most significant challenges being the processing of thru-hole components on high thermal mass PCBs having the potential to exceed 20 layers in thicknesses and have copper mass contents of over 40oz. High thermal mass PCBs, coupled with the use of mixed technologies, decreased component spacing, and the change from Tin Lead Solder to Lead Free Alloys has lead many manufacturing facilities to purchase advanced soldering equipment to process challenging assemblies with a high degree of repeatability.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2021-09-29 13:35:21.0
In PCB circuit assemblies the trend is moving to more SMD components with finer pitch connections. The majority of the assemblies still have a small amount of through hole (THT) components. Some of them can't withstand high reflow temperatures, while others are there because of their mechanical robustness. In automotive applications these THT components are also present. Many products for cars, including steering units, radio and navigation, and air compressors also use THT technology to connect board-to-board, PCB's to metal shields or housings out of plastic or even aluminium. This is not a simple 2D plain soldering technology, as it requires handling, efficient thermal heating and handling of heavy (up to 10 kg) parts. Soldering technology becomes more 3D where connections have to be made on different levels. For this technology robots using solder wire fail because of the spattering of the flux in the wires and the long cycle time. In wave soldering using pallets the wave height is limited and pin in paste reflow is only a 2D application with space limitations. Selective soldering using dedicated plates with nozzles on the solder area is the preferred way to make these connections. All joints can be soldered in one dip resulting in short cycle times. Additional soldering on a small select nozzle can make the system even more flexible. The soldering can only be successful when there is enough thermal heat in the assembly before the solder touches the board. A forced convection preheat is a must for many applications to bring enough heat into the metal and board materials. The challenge in a dip soldering process is to get a sufficient hole fill without bridging and minimize the number of solder balls. A new cover was designed to improve the nitrogen environment. Reducing oxygen levels benefits the wetting, but increases the risk for solder balling. Previous investigations showed that solder balling can be minimized by selecting proper materials for solder resist and flux.
Technical Library | 2021-05-26 00:53:26.0
This paper describes a copper electroplating enabling technology for filling microvias. Driven by the need for faster, smaller and higher performance communication and electronic devices, build-up technology incorporating microvias has emerged as a viable multilayer printed circuit manufacturing technology. Increased wiring density, reduced line widths, smaller through-holes and microvias are all attributes of these High Density Interconnect (HDI) packages. Filling the microvias with conductive material allows the use of stacked vias and via in pad designs thereby facilitating additional packaging density. Other potential design attributes include thermal management enhancement and benefits for high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over alternative via plugging techniques. The features, development, scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling processes, including chemistry and equipment, are described.
