Technical Library | 2024-08-20 00:40:08.0
In electronics manufacturing, 'Underfill' refers to a material that is applied to fill the gap between a semiconductor device, such as flip-chip assemblies, Ball Grid Arrays (BGA), or Chip Scale Packages (CSP), and the substrate, such as a PCB or flex circuit.
Technical Library | 2014-06-19 18:13:23.0
For high-density electronic packaging,the application of flip-chip solder joints has been well received in the microelectronics industry. High-lead(Pb) solders such as Sn5Pb95 are presently granted immunity from the RoHS requirements for their use in high-end flip-chip devices, especially in military applications. In flip-chip technology for consumer electronic products, organic substrates have replaced ceramic substrates due to the demand for less weight and low cost. However, the liquidus temperatures of high-Pb solders are over 300°C which would damage organic substrates during reflow because of the low glass transition temperature. To overcome this difficulty, the composite solder approach was developed...
Technical Library | 2007-10-10 23:23:40.0
Process engineers, who are seeking to achieve the most effective and reproducible thermal transfer process, look to today's forced convection ovens for applications such as flipchip, BGA, and lead-free soldering. A forced convection process to maximize thermal uniformity can be best accomplished by employing static pressure generation in what's known as "closed loop convection".
Technical Library | 2010-01-06 22:27:03.0
Increased functionality and performance requirements for microprocessors and ASICs have resulted in a trend to package these devices in the flip-chip BGA form factor (FCBGA). Because these devices use in excess of 40-100 Watts of power, their packages must dissipate heat in an extremely efficient manner. Most semiconductor companies have developed some type of thermally enhanced FCBGA package that provides heat dissipation through the back of the die to a heat spreader.
Technical Library | 2008-02-26 15:02:19.0
More and more chip packages need multi-GHz RF structures to meet their performance targets. The ideal chip package needs to combine RF features with Digital features for these applications. They drive low-loss, controlled impedance transmission lines, flexibility in assigned signal and power layers, and clearances of various shapes in power layers. Building these features in a chip package is difficult without making the stack-up very thick or compromising the reliability of the product. In the present paper, we have designed and built a flip-chip package test vehicle (TV) to make new RF structures, using Z-axis interconnection (Zinterconnect) building blocks.
Technical Library | 2017-06-22 17:11:53.0
C-mode scanning acoustic microscopy (C-SAM) is a non-destructive inspection technique showing the internal features of a specimen by ultrasound. The C-SAM is the preferred method for finding “air gaps” such as delamination, cracks, voids, and porosity. This paper presents evaluations performed on various advanced packages/assemblies especially flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. For comparison, representative x-ray images of the assemblies were also gathered to show key defect detection features of the two non-destructive techniques.
Technical Library | 2013-01-03 20:27:54.0
Electronics assemblies with large flip-chip BGA packages can be prone to either pad cratering or brittle intermetallic (IMC) failures under excessive PCB bending. Pad cratering cracks are not detected by electrical testing or non-destructive inspection methods, yet they pose a long term reliability risk since the cracks may propagate under subsequent loads to cause electrical failure. Since the initiation of pad cratering does not result in an instantaneous electrical signature, detecting the onset of this failure has been challenging. An acoustic emission methodology was recently developed by the authors to detect the onset of pad cratering. The instantaneous release of elastic energy associated with the initiation of an internal crack, i.e., Acoustic Emission (AE), can be monitored to accurately determine the onset of both pad cratering and brittle intermetallic (IMC) failures.
Technical Library | 2007-10-25 18:39:07.0
More and more substrate designs require signals paths that can handle multi-gigahertz frequencies [1-3]. The challenges for organic substrates, in meeting these electrical requirements, include using high-speed, low-loss materials, manufacturing precise structures and making a reliable finished product. A new substrate technology is presented that addresses these challenges.
Technical Library | 2009-07-22 18:33:41.0
This paper deals with the thermal effects of joule heating in a high interconnect density, thin core, buildup, organic flip chip substrate. The 440 μm thick substrate consists of a 135 μm thick core with via density of about 200 μm. The typical feature sizes in the substrate are 50 micron diameter vias is the core/buildup layers and 12 micron thick metal planes. An experimental test vehicle is powered with current and the temperature rise was measured. A numerical model was used to simulate the temperature rise in the TV.
Technical Library | 2013-03-14 17:19:28.0
Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings.
