Technical Library | 2019-06-17 15:09:43.0
Very often pick and place machines are programmed using CAD data. This data increases the accuracy, precision, and repeatability of its component placement objectives. CAD data makes fine pitch and small component assemblies repeatable, but cannot adjust to a particular board unless it is exactly the same size and shape of the original board used for programming. The process by which printed circuit boards (PCBs) are made only allows some minor changes inboard size and shape, but these small differences are enough for parts to be misplaced. For this reason we use fiducial marks to increase the chances of precise component alignment.
Technical Library | 2014-08-19 16:07:15.0
Warpage management consists of planning, measuring, analyzing, sharing, and reacting to data related to the surface shapes of electronics components as they change throughout the reflow assembly process. Leading semiconductor manufacturers have had warpage management systems in place for ten years or more, mainly because microchip package warpage must be understood and compensated for in order to attain high assembly yields. Similarly, newer device architectures such as package-on-package and system-on-a-chip are sensitive to warpage-related assembly issues, and companies involved in the manufacture and assembly of these devices tend to have the most advanced warpage management programs.
Technical Library | 2017-09-28 16:36:33.0
These nano-coatings also refine the solder paste brick shape giving improved print definition. These two benefits combine to help the solder paste printing process produce an adequate amount of solder paste in the correct position on the circuit board pads. Today, stencil aperture area ratios from 0.66 down to 0.40 are commonly used and make paste printing a challenge. This paper presents data on small area ratio printing for component designs including 01005 Imperial (0402 metric) and smaller 03015 metric and 0201 metric chip components and 0.3 mm and 0.4 mm pitch micro BGAs.
Technical Library | 2014-08-19 15:39:13.0
Understanding warpage of package attach locations on PCBs under reflow temperature conditions is critical in surface mount technology. A new industry standard, IPC 9641, addresses this topic directly for the first time as an international standard.This paper begins by summarizing the sections of the IPC 9641 standard, including, measurement equipment selection, test setup and methodology, and accuracy verification. The paper goes further to discuss practical implementation of the IPC 9641 standards. Key advantages and disadvantages between available warpage measurement methods are highlighted. Choosing the correct measurement technique depends on requirements for warpage resolution, data density, measurement volume, and data correlation. From industry experience, best practice recommendations are made on warpage management of PCB land areas, covering how to setup, run, analyze, and report on local area PCB warpage.The release of IPC 9641 shows that flatness over temperature of the package land area on the PCB is critical to the SMT industry. Furthermore, compatibility of shapes between attaching surfaces in SMT, like a package and PCB, will be critical to product yield and quality in years to come.
Technical Library | 2023-06-12 18:33:29.0
This paper presents a real-time predictive approach to improve solder paste stencil printing cycle decision making process in surface mount assembly lines. Stencil cleaning is a critical process that influences the quality and efficiency of printing circuit board. Stencil cleaning operation depends on various process variables, such as printing speed, printing pressure, and aperture shape. The objective of this research is to help efficiently decide stencil printing cleaning cycle by applying data-driven predictive methods. To predict the printed circuit board quality level, a recurrent neural network (RNN) is applied to obtain the printing performance for the different cleaning aging. In the prediction model, not only the previous printing performance statuses are included, but also the printing settings are used to enhance the RNN learning. The model is tested using data collected from an actual solder paste stencil printing line. Based on the predicted printing performance level, the model can help automatically identify the possible cleaning cycle in practice. The results indicate that the proposed model architecture can predictively provide accurate solder paste printing process information to decision makers and increase the quality of the stencil printing process.
Technical Library | 2021-06-15 18:40:53.0
The jet printing of a dense mixed non-Newtonian suspension is based on the rapid displacement of fluid through a nozzle, the forming of a droplet and eventually the break-off of the filament. The ability to model this process would facilitate the development of future jetting devices. The purpose of this study is to propose a novel simulation framework and to show that it captures the main effects such as droplet shape, volume and speed. In the framework, the time dependent flow and the fluid-structure interaction between the suspension, the moving piston and the deflection of the jetting head is simulated. The system is modelled as a two phase system with the surrounding air being one phase and the dense suspension the other. Hence, the non-Newtonian suspension is modelled as a mixed single phase with properties determined from material testing. The simulations were performed with two coupled in-house solvers developed at Fraunhofer-Chalmers Centre; IBOFlow, a multiphase flow solver and LaStFEM, a large strain FEM solver. Jetting behaviour was shown to be affected not only by piston motion and fluid rheology, but also by the energy loss in the jetting head. The simulation results were compared to experimental data obtained from an industrial jetting head.
Fraunhofer-Chalmers Research Centre for Industustrial Mathematics
Technical Library | 2020-09-02 22:02:13.0
With the adoption of Wafer Level Packages (WLP) in the latest generation mobile handsets, the Printed Circuit Board (PCB) industry has also seen the initial steps of High Density Interconnect (HDI) products migrating away from the current subtractive processes towards a more technically adept technique, based on an advanced modified Semi Additive Process (amSAP). This pattern plate process enables line and space features in the region of 20um to be produced, in combination with fully filled, laser formed microvias. However, in order to achieve these process demands, a step change in the performance of the chemical processes used for metallization of the microvia is essential. In the electroless Copper process, the critical activator step often risks cross contamination by the preceding chemistries. Such events can lead to uncontrolled buildup of Palladium rich residues on the panel surface, which can subsequently inhibit etching and lead to short circuits between the final traces. In addition, with more demands being placed on the microvia, the need for a high uniformity Copper layer has become paramount, unfortunately, as microvia shape is often far from ideal, the deposition or "throw" characteristics of the Copper bath itself are also of critical importance. This "high throwing power" is influential elsewhere in the amSAP technique, as it leads to a thinner surface Copper layer, which aids the etching process and enables the ultra-fine features being demanded by today's high end PCB applications. This paper discusses the performance of an electroless Copper plating process that has been developed to satisfy the needs of challenging amSAP applications. Through the use of a radical predip chemistry, the formation, build up and deposition of uncontrolled Pd residues arising from activator contamination has been virtually eradicated. With the adoption of a high throwing power Copper bath, sub 30um features are enabled and microvia coverage is shown to be greatly improved, even in complex via shapes which would otherwise suffer from uneven coverage and risk premature failure in service. Through a mixture of development and production data, this paper aims to highlight the benefits and robust performance of the new electroless Copper process for amSAP applications
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