Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
Technical Library | 2016-02-04 19:11:47.0
In a typical mechatronic manufacturing functional test setup, actual load simulations are usually done by connecting the DUT outputs to power or ground in order to establish either a high or low side driver. Each output is connected with different load and the test will either be sequential or concurrent. At lower power levels, these can usually be managed with general purpose switches. However, when it comes to higher power levels of currents more than 5 amps, such switching and loading might pose a greater challenge. Furthermore, critically in the manufacturing line, the tradeoff between cost and test time would have a great influence on the test strategy.This paper will present some key points to design a cost effective high power switching and load management solution.
Technical Library | 2018-12-12 22:20:22.0
Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard, readily available device packaging methods in which high-density packaging is achieved by: (1) using standard "packaged" memory devices, (2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads, stacked either 2-high or 4-high, and integrated into a single dual-flat-no-lead (DFN) package.
Technical Library | 2021-09-15 19:00:35.0
This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a lifecycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.
Technical Library | 2012-12-14 14:25:37.0
The popularity of low voltage technologies has grown significantly over the last decade as semiconductor device manufacturers have moved to satisfy market demands for more powerful products, smaller packaging, and longer battery life. By shrinking the size of the features they etch into semiconductor dice, IC manufacturers achieve lower costs, while improving speed and building in more functionality. However, this move toward smaller features has lead to lower breakdown voltages and increased opportunities for component overstress and false failures during in-circuit test.
Technical Library | 2020-03-19 00:23:15.0
In this study, the question was how to perform statistically reliable robust- ness tests for the non-contact drop-on-demand printing of functional fluids, such as solder paste and conductive adhesives. The goal of this study was to develop a general method for hypothesis testing when robustness tests are performed. The main problem was to determine if there was a statistical difference between two means or proportions of jet printing devices. In this study, an example of jetting quality variation was used when comparing two jet printing ejector types that differ slightly in design. We wanted to understand if the difference in ejector design can impact jetting quality by performing robustness tests. and thus answer the question, "Can jetting differences be seen between ejector design 1 and design 2"?
Technical Library | 2020-12-10 15:49:40.0
Electronic assemblies should have longer and longer service life. Today there are partially demanded 20 years of functional capability for electronics for automotive application. On the other hand, smaller components, such as resistors of size 0201, are able to endure an increasing number of thermal cycles until fail of solder joints, so these are tested sometimes up to 4000 cycles. But testing until the end of life is essential for the determination of failure rates and the prognosis of reliability. Such tests require a lot of time, but this is often not available in developing of new modules. A further acceleration by higher cycle temperatures is usually not possible, because the materials are already operated at the upper limit of the load. However, the duration can be shortened by the use of liquids for passive tests, which allow faster temperature changes and shorter dwell times because of better heat transfer compared to air. The question is whether such tests lead to comparable results and what failure mechanisms are becoming effective. The same goes for active temperature cycles, in which the components itself are heated from inside and the substrate remains comparatively cold. This paper describes the various accelerated temperature cycling tests, compares and evaluates the related degradation of solder joints.
Technical Library | 2023-02-13 19:14:03.0
Technology Focus: Develop and evaluate nanoparticle filled conformal coatings designed to provide long term whisker penetration resistance and coverage on tin rich metal surfaces prone to whisker growth in commercial lead-free electronics used in modern DoD systems. Research Objectives: Identify the fundamental mechanisms by which conformal coatings provide long-term tin whisker penetration resistance and inhibit nucleation/growth. Correlate mechanical properties and coverage thickness to whisker penetration resistance. Project Progress and Results: Functionalized nanosilica and non-functional nanoalumina enhanced polyurethane conformal coatings have shown improved spray coating coverage characteristics and crack resistance during thermal cycling fatigue testing. Lead-free assembly whisker mitigation validation testing is in process. Technology Transition: Current project partners provide coating materials to industry. SERDP test data will be considered during updates to the DoD adopted IPC standards for coating materials and coverage.
Technical Library | 2015-01-28 17:39:34.0
Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology.
Technical Library | 2010-03-18 14:02:03.0
Selecting products that have been qualified by industry standards for use in printed circuit board assembly processes is an accepted best practice. That products which have been qualified, when used in combinations not specifically qualified, may have resultant properties detrimental to assembly function though, is often not adequately understood. Printed circuit boards, solder masks, soldering materials (flux, paste, cored wire, rework flux, paste flux, etc.), adhesives, and inks, when qualified per industry standards, are qualified using very specific test methods which may not adequately mimic the assembly process ultimately used.
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