Technical Library | 2013-01-17 15:34:33.0
The use of an electroless nickel, immersion gold (ENIG) surface finish comes with the inherent potential risk of Black Pad failures that can cause fracture embrittlement at the interface between the solder and the metal pad. As yet, there is no conclusive agreed solution to effectively eliminate Black Pad failures. The case studies presented are intended to add to the understanding of the Black Pad failure mechanism and to identify both the plating and the subsequent assembly processes and conditions that can help to prevent the likelihood of Black Pad occurring.
Technical Library | 2017-08-10 01:23:22.0
This paper demonstrates the high frequency performance and thermo-mechanical reliability of through vias with 25 μm diameter at 50 μm pitch in 100 μm thin glass substrates. Scaling of through via interconnect diameter and pitch has several electrical performance advantages for high bandwidth 2.5D interposers as well as mm-wave components for 5G modules.
Technical Library | 2015-12-23 16:57:27.0
The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.
Technical Library | 2021-07-13 19:51:10.0
Flexible electronics refers to a class of lightweight, flexible and electronic sensing components and electronic devices built on stretchable substrates1 that are used (and can be used) for a broad set of products and applications such as displays and sensors. The most prominent characteristic is that they can bend in contrast to electronic systems built in rigid materials. They are manufactured on flexible plastic substrates, such as polyamide, PEEK2 or transparent conductive polyester films3, or other materials such as paper, textile, or thin glass. The term flexible also refers to the roll-to-roll manufacturing process.
European Commission - Executive Agency for Small and Medium-sized Enterprises (EASME)
Technical Library | 2021-12-21 23:15:44.0
High Density Interconnect (HDI) technologies are being used widely in Asia and Europe in consumer electronics for portable wireless communication and computing, digital imaging, and chip packaging. Although North America lags behind in developing process capability for this technology, HDI will become a significant business segment for North America. For this to happen, the printed circuit board shops will have to become process capable in fabricating fine lines and spaces, and also be capable in forming and plating microvias.
Technical Library | 2019-11-07 08:59:14.0
Inductors realized with high permeable MnZn ferrite require, unlike iron-powder cores with an inherent dis-tributed gap, a discrete air gap in the magnetic circuit to prevent saturation of the core material and/or tune the inductance value. This large discrete gap can be divided into several partial gaps in order to reduce the air gap stray field and consequently the proximity losses in the winding. The multi-gap core, realized by stacking several thin ferrite plates and inserting a non-magnetic spacer material between the plates, however, exhibits a substan-tial increase in core losses which cannot be explained from the intrinsic properties of the ferrite. In this paper, a comprehensive overview of the scientific literature regarding machining induced core losses in ferrite, dating back to the early 1970s, is provided which suggests that the observed excess core losses could be attributed to a deterioration of ferrite properties in the surface layer of the plates caused by mechanical stress exerted during machining.
Technical Library | 2020-10-18 19:35:05.0
Interconnect reliability especially in BGA solder joints and compliant pins are subjected to design parameters which are very critical to ensure product performance at pre-defined shipping condition and user environment. Plating thickness of compliant pin and damping mechanism of electronic system design are key successful factors for this purpose. In additional transportation and material handling process of a computer server system will be affected by shock under certain conditions. Many accessories devices in the server computer system tend to become loose resulting in poor contact or solder intermittent interconnect problems due to the shock load from the transportation and material handling processes.
Technical Library | 2020-11-15 21:01:24.0
ENIG, electroless nickel immersion gold is now a well-regarded finish used to enhance and preserve the solder-ability of copper circuits. EPIG, electroless palladium immersion gold, is a new surface finish also for enhancing and preserving solder-ability but with the advantage of eliminating Electroless Nickel from the deposit layer. This feature has become increasingly important with the increasing use of high frequeny PWB designs whereby nickel's magnetic properties are detrimental. We examine these two finishes and their respective soldering characteristics as plated and after steam aging and offer an explanation for the performance deviation.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2017-09-07 13:56:11.0
As a surface finish for PCBs, Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) was selected over Electroless Nickel/Immersion Gold (ENIG) for CMOS image sensor applications with both surface mount technology (SMT) and gold ball bonding processes in mind based on the research available on-line. Challenges in the wire bonding process on ENEPIG with regards to bondability and other plating related issues are summarized.
