Technical Library: glass and plate (Page 3 of 3)

Long Term Thermal Reliability of Printed Circuit Board Materials

Technical Library | 2016-09-15 17:10:40.0

This paper describes the purpose, methodology, and results to date of thermal endurance testing performed at the company. The intent of this thermal aging testing is to establish long term reliability data for printed wiring board (PWB) materials for use in applications that require 20+ years (100,000+ hours) of operational life under different thermal conditions. Underwriters Laboratory (UL) testing only addresses unclad laminate (resin and glass) and not a fabricated PWB that undergoes many processing steps, includes copper and plated through holes, and has a complex mechanical structure. UL testing is based on a 5000 hour expected operation life of the electronic product. Therefore, there is a need to determine the dielectric breakdown / degradation of the composite printed circuit board material and mechanical structure over time and temperature for mission critical applications.

Amphenol Printed Circuit Board Technology

Advances in Conductive Inks across Multiple Applications and Deposition Platforms

Technical Library | 2012-12-27 14:35:29.0

Printed Electronics is generally defined as the patterning of electronic materials, in solution form, onto flexible substrates, omitting any use of the photolithography, etching, and plating steps commonly found within the Printed Circuit Board (PCB) industry. The origins of printed electronics go back to the 1960s, and close variants of several original applications and market segments remain active today. Through the 1980s and 1990s Printed Electronic applications based on Membrane Touch Switch and Electroluminescent lighting technologies became common, and the screen printed electronic materials used then have formed the building blocks for many of the current and emerging technologies and applications... First published in the 2012 IPC APEX EXPO technical conference proceedings.

DuPont

Anisotropic grain growth and crack propagation in eutectic microstructure under cyclic temperature annealing in flip-chip SnPb composite solder joints

Technical Library | 2014-06-19 18:13:23.0

For high-density electronic packaging,the application of flip-chip solder joints has been well received in the microelectronics industry. High-lead(Pb) solders such as Sn5Pb95 are presently granted immunity from the RoHS requirements for their use in high-end flip-chip devices, especially in military applications. In flip-chip technology for consumer electronic products, organic substrates have replaced ceramic substrates due to the demand for less weight and low cost. However, the liquidus temperatures of high-Pb solders are over 300°C which would damage organic substrates during reflow because of the low glass transition temperature. To overcome this difficulty, the composite solder approach was developed...

National Chiao Tung University

Development of a Consistent and Reliable Thermal Conductivity Measurement Method, Adapted to Typical Composite Materials Used in the PCB Industry

Technical Library | 2017-05-04 17:35:01.0

Most of today's printed circuit board base materials are anisotropic and it is not possible to use a simple method to measure thermal conductivity along the different axis, especially when a good accuracy is expected. Few base material suppliers' datasheet show X, Y and Z thermal conductivities. In most cases, a single value is given, moreover determined with a generic methodology, and not necessarily adapted to the reality of glass-reinforced composites with a strong anisotropy.After reminding of the fundamentals in thermal science, this paper gives an overview of the state-of the art in terms of thermal conductivity measurement on PCB base materials, and some typical values. It finally proposes an innovative method called transient fin method, and associated test sample, to perform reliable and consistent in plane thermal conductivity measurement on anisotropic PCB base materials.

CIMULEC

Moisture Measurements in PCBs and Impact of Design on Desorption Behaviour

Technical Library | 2018-09-21 10:12:53.0

Moisture accumulates during storage and industry practice recommends specific levels of baking to avoid delamination. This paper will discuss the use of capacitance measurements to follow the absorption and desorption behaviour of moisture. The PCB design used in this work, focused on the issue of baking out moisture trapped between copper planes. The PCB was designed with different densities of plated through holes and drilled holes in external copper planes, with capacitance sensors located on the inner layers. For trapped volumes between copper planes, the distance between holes proved to be critical in affecting the desorption rate. For fully saturated PCBs, the desorption time at elevated temperatures was observed to be in the order of hundreds of hours. Finite difference diffusion modelling was carried out for moisture desorption behaviour for plated through holes and drilled holes in copper planes. A meshed copper plane was also modelled evaluating its effectiveness for assisting moisture removal and decreasing bake times. Results also showed, that in certain circumstances, regions of the PCB under copper planes initially increase in moisture during baking.

National Physical Laboratory

Approaches to Overcome Nodules and Scratches on Wire Bondable Plating on PCBs

Technical Library | 2020-08-27 01:22:45.0

Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.

Teledyne DALSA

Difference between Neutral and Acid Salt Spray Corrosion Test

Technical Library | 2019-12-13 00:39:29.0

Salt spray corrosion chamber can test the ability of material and its protective layer to resist salt mist corrosion, or compare the process quality of similar protective layers, at the same time; this equipment is suitable for parts, electronic components, protective layer of metal material and other industrial products. Salt spray test is divided into neutral and acid test. What is the difference between neutral and acid in salt spray test? First, the temperature applied in the test method is different: Neutral test: a. Laboratory:35°C ±1°C, b. Saturated air drums:47°C ±1°C Acid test: a. Laboratory:50°C ±1°C, b. Saturated air drums:63°C ±1°C Second, the production material is different,neutral test chamber adoptes the traditional PVC plates, acid test chamber asopts PP sheet,which is more high temperature resistance and suits strong acid test. Third. Different test methods satisfied Neutral salt spray chamber according to GB/T 2423.17-2008, GB/T 2423.18-2000, salt spray test method and GB/T 10125-1997, GB/T 10587-2006, GB10593.2-1990, GB/T 1765-1979, GB/T 1771-2007, GB/T 12967.388, GB/T 1705.8-2008, etc. In addition to the test methods specified in the national standard, acid salt spray chamber also needs to expand the standard setting such as IEC,MIL,DIN,ASTM,IS,CNS. Last, Comparison of neutral test solutions China: NaCI distilled water solution NaCI mass concentration (50 ±5) g ≤ l pH value 6.5 ≤ 7.2 United States: distilled water solution NaCI mass concentration 5% ±1% pH value 6.5 ≤ 7.2 Germany: NaCI distilled water solution NaCI mass concentration (50 ±5) g ≤ l pH value 6.5 ≤ 7.2 Japan: NaCI distilled water solution NaCI mass concentration 5% ±1% pH pH value 6.5 ~ 7.2 France: NaCI distilled water solution NaCI mass concentration 5% pH 6.5 ≤ 7.2 https://climatechambers.com/articles&latestnews/difference-between-neutral-and-acid-salt-spray-corrosion-test.html

Symor Instrument Equipment Co.,Ltd

Review of Interconnect Stress Testing Protocols and Their Effectiveness in Screening Microvias

Technical Library | 2016-11-30 15:53:15.0

The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.

Raytheon

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