Technical Library | 2001-04-24 10:44:24.0
This paper reviews the possible implementations of the Micro Via Technology within the Mentor Graphic's Board Station environment, specifically within the Librarian, Layout and Fablink applications. In this context, the definition of a Micro Via is constrained to Board Station’s support of such technology and contains only generalized descriptions of the manufacturing processes that require Micro Vias.
Technical Library | 2010-11-16 12:06:38.0
The Net Tie is a component type which allows for shorting together various nets in a design. The graphic for the symbol can be as simple as two component pins representing a virtual component between nets or as complex as mutipul pins (as many as desired)
Technical Library | 1999-05-07 10:20:34.0
Media (video, audio, graphics, communication) applications present a unique opportunity for performance boost via use of Single Instruction Multiple Data (SIMD) techniques. While several of the computeintensive parts of media applications benefit from SIMD techniques, a significant portion of the code still is best suited for general purpose instruction set architectures. MMX™ technology extends the Intel Architecture (IA), the industry's leading general purpose processor architecture, to provide the benefits of SIMD for media applications.
Technical Library | 2015-04-08 11:10:47.0
An electronic schematic describes the electrical connectivity of a piece of equipment or an entire system. It is made up of symbols that represent individual components and contains electrical and mechanical information and their related connectivity, along with other important data. Information contained within the schematic is packaged into a printed circuit board (PCB) where the mechanical footprint is placed onto the board and connectivity information is graphically displayed. The more accurate the information contained in the schematic is and the clearer it is presented, the more it contributes to a robust printed circuit board.
Technical Library | 2019-01-30 21:20:47.0
Due to the arrayed nature of the Computed Tomography (CT) Detector, high density area array interconnect solutions are critical to the functionality of the CT detector module. Specifically, the detector module sensor element, hereby known as the Multi-chip module (MCM), has a 544 position BGA area array pattern that requires precise test stimulation. A novel pogo-pin block array and corresponding motorized test socket has been designed to stimulate the MCM and acquire full functional test data. (...) This paper and presentation will focus on the socket design challenges and also key learnings from the design that can be applied to general test systems, including reliability testing. The secondary focus will be on the overall data collection and graphical user interface for the test equipment.
Technical Library | 2001-04-24 10:41:53.0
Tau models describe the timing and functional information of component interfaces. Timing information specifies the delay in placing values on output signals and the timing constraints (set-up/hold, pulse-width) on input signals of a component. Functional information, through a finite state machine (FSM), specifies when output signal values change, when input signal values are latched, and how output values are determined as a function of input values.
Technical Library | 2009-04-16 22:38:55.0
The worldwide electronics industry has sales of $750 billion, two thirds of which is accounted for by PCB assembly. PCB manufacturing is characterised by an obsessive drive for increased productivity in the context of three significant industry drivers: shorter product lifecycles, more complexity, outsourcing
Technical Library | 2012-04-19 21:50:46.0
Presented at IPC Apex 2012. Working through the New Product Introduction (NPI) flow between product design and manufacturing is usually a challenging process, with both parties being experts in their own fields and inextricably linked in the flow of g
Technical Library | 2001-04-24 10:38:38.0
Many PCB designers are interested in taking advantage of Multichip Modules, but are unfamiliar with the technology. While the design process is very much the same, MCM manufacturing processes vary dramatically. MCM routing requirements are dictated by the manufacturing process and types of components. Components mounted on MCM substrates are predominantly, if not exclusively, bare chips. As a result, the component body and I/O pins are no longer constrained to industry standard pin counts and form factors as are packaged components...
Technical Library | 2001-04-24 10:47:02.0
Board-level circuits today routinely run at speeds of 100 MHz or more and are composed of dozens of complex interacting VLSI components. To design such circuits in a timely and correct manner it is necessary to pay close attention to circuit timing early in the design cycle. At fast clock speeds, managing component and interconnect propagation delay becomes a key aspect of circuit design. It is imperative that the critical paths on a circuit and the slack available for interconnect delay consumption be identified early, and drive subsequent stages in the design flow.
