Technical Library | 2016-04-14 13:49:44.0
A system level test, usually built-in test (BIT), determines that one or more subsystems are faulty. These subsystems sent to the depot or factory repair facility, called units under test (UUTs) often pass that test, an event we call No-Fault-Found (NFF). With more-and more electronics monitored by BIT, it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA), cannot duplicate (CNDs)or retest OK (RTOK) events. NFFs at the depot are caused by FAs, CNDs, RTOKs as well as a number of other complications. Attempting to repair NFF scan waste precious resources, compromise confidence in the product, create customer dissatisfaction, and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action at the system level are invalid. NFFs can be caused by real failures or may be a result of system level false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs.This paper will shed some light on this trade-off. Finally, we will explore approaches for dealing with the NFF issue in a cost effective manner.
Technical Library | 2018-10-24 18:04:12.0
Polymer Thick Film (PTF)-based printed electronics (aka Printed Electronics) has improved in durability over the last few decades and is now a proven alternative to copper circuitry in many applications once thought beyond the capability of PTF circuitry. This paper describes peak performance and areas for future improvement.State-of-the-art PTF circuitry performance includes the ability to withstand sharp crease tests, 85C/85%RH damp heat 5VDC bias aging (silver migration), auto seat durability cycling, SMT mandrel flexing, and others. The IPC/SGIA subcommittee for Standards Tests development has adopted several ASTM test methods for PTF circuitry and is actively developing needed improvements or additions. These standards are described herein. Advantages of PTF circuitry over copper include: varied conductive material compositions, lower cost and lower environmental impact. Necessary improvements include: robust integration of chip and power, higher conductivity, and fine line multi-layer patterning.
Technical Library | 2019-02-27 15:23:47.0
A study was performed to investigate, evaluate and qualify new reworkable underfill materials to be used primarily with ball grid arrays (BGAs), Leadless SMT devices, QFNs, connectors and passive devices to improve reliability. The supplier of the sole source, currently used underfill, has indicated they may discontinue its manufacture in the near future. The current underfill material is used on numerous circuit card assemblies (CCAs) at several sites and across multiple programs/business areas. In addition, it is used by several of our contract CCA suppliers.The study objectives include evaluation of material properties for down select, dispensability and rework evaluation for further down select, accelerated life testing for final selection and qualification; and process development to implement into production and at our CCA suppliers. The paper will describe the approach used, material property test results and general findings relative to process characteristics and rework ability.
Technical Library | 2011-11-25 16:07:47.0
The article presents virtual and real investigations related to current capacity and fusing of PCB traces in high power applications and is based on a scientific paper delivered by authors at SIITME 2010 in Romania. The reason of performing the research a
Technical Library | 2016-11-30 15:53:15.0
The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.
Technical Library | 2012-11-29 14:23:58.0
1000 units per day) production environment presents challenging technical, logistic and cost obstacles that are usually more complex than those encountered at the inspection (automated optical inspection) and the manufacturing process test step (in-circuit test).
Technical Library | 2013-11-21 12:01:11.0
Previous experimentation on a highly miniaturized and densely populated SMT assembly revealed the optimum stencil alloy and flux-repellent coating for its stencil printing process. Production implementation of the materials that were identified in the study resulted in approximately 5% print yield improvement across all assemblies throughout the operation, validating the results of the initial tests. A new set of studies was launched to focus on the materials themselves, with the purpose of optimizing their performance on the assembly line (...) Results of the prior tests are reviewed, and the new test vehicle, experimental setup and results are presented and discussed.
Technical Library | 2022-01-26 15:22:33.0
Reliability of conformal coatings used to mitigate tin whisker growth depends on their ability to contain tin whiskers. Two key material properties required to assess the reliability of a polyurethane coating are documented experimentally: adhesion strength and puncture strength. A modified blister test using a predefined blister area is employed to assess the adhesion strength and a puncture test is employed to evaluate the puncture strength of the coating. After measuring the properties at time zero, the coatings are subjected to accelerated testing conditions (high temperature/humidity storage and temperature cycling) and the degradations of the coating properties are documented.
Technical Library | 2011-06-23 18:44:23.0
Over the last few years, there has been an increase in the evaluation and use of halogen-free soldering materials. In addition, there has been increased scrutiny into the level of halogens and refinement of the definition and testing of halogen-free solde
Technical Library | 1999-08-05 10:27:43.0
This document is an update to the 1994 Quality and Reliability Roadmap issued in support of the 1994 National Technology Roadmap for Semiconductors. This report revisits the challenges, constraints, priorities, and research needs pertaining to quality and reliability issues. It also provides key project proposals that must be implemented to address concerns about reliability attainment and defect learning. An expanded section on test-to-test, diagnostics, and failure analysis; an edited version of the Product Analysis Forum Roadmap; and an appendix containing a draft report highlighting reliability issues is included.
