Technical Library | 2013-02-08 22:56:47.0
Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.
Technical Library | 2013-06-20 14:33:12.0
With today's consumer technologies driving the need for denser and more compact devices, the assembly process for surface mounted devices has becoming increasingly more difficult. With the mixture of components requiring a broader range of print deposition volume, various techniques are in use in an attempt to ensure consistent and appropriate paste volume is achieved. Some of these techniques include step etching a stencil locally on a targeted device, promoting electroformed smooth wall nickel stencils, through to laser cutting newer grade stencil materials. This paper focuses on the relevant attributes that affect the properties of solder paste release and introduces the effects of surface free energy with respect to key elements that make up the stencil printing process.
Technical Library | 2014-09-18 16:48:26.0
Two major drivers in electronic industry are electrical and mechanical miniaturization. Both induce major changes in the material selection as well as in the design. Nevertheless, the mechanical and thermal reliability of a Printed Circuit Board (PCB) has to remain at the same high level or even increase (e.g. multiple lead-free soldering). To achieve these reliability targets, extensive testing has to be done with bare PCB as well as assembled PCB. These tests are time consuming and cost intensive. The PCBs have to be produced, assembled, tested and finally a detailed failure analysis is required to be performed.This paper examines the development of our concept and has the potential to enable the prediction of the lifetime of the PCB using accelerated testing methods and finite element simulations.
Technical Library | 2015-02-27 17:06:01.0
The drive towards fine pitch technology also affects the soldering processes. Selective soldering is a reliable soldering process for THT (through hole) connectors and offers a wide process window for designers. THT connectors can be soldered on the top and bottom side of boards, board in board, PCBs to metal shields or housing out of plastic or aluminum are today's state of the art. The materials that are used to make the solder connections require higher temperatures. Due to the introduction of lead-free alloys, the boards need more heat to get the barrels filled with solder. This not only affects the properties of the flux and components, but the operation temperatures of solder machines become higher (...)First the impact of temperature will be discussed for the separate process steps and for machine tooling. In the experimental part measurements are done to verify the accuracy that can be achieved using today's selective soldering machines. Dedicated tooling is designed to achieve special requirements with respect to component position accuracy.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2017-10-16 15:03:32.0
The miniaturization and advancement of electronic devices have been the driving force of design, research and development, and manufacturing in the electronic industry. However, there are some issues occurred associated with the miniaturization, for examples, warpage and reliability issues. In order to resolve these issues, a lot of research and development have been conducted in the industry and university with the target of moderate melting temperature solder alloys such as m.p. 280°C. These moderate temperature alloys have not resolve these issues yet due to the various limitations. YINCAE has been working on research and development of the materials with lower temperature soldering for higher temperature application. To meet this demand, YINCAE has developed solder joint encapsulant paste to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. This solder joint encapsulant paste can be used in typical lead-free profile and after reflow the application temperature can be up to over 300C, therefore it also eliminates red glue for double side reflow process. In this paper, we will discuss the reliability such as strength of solder joints, drop test performance and thermal cycling performance using this solder joint encapsulant paste in detail.
Technical Library | 2021-07-13 19:59:34.0
We have investigated the processing of lead-zirconate-titanate-based thick films by inkjet printing Pb (Zr0.53Ti0.47)0.98Nb0.02O3 with a 6 mol% excess of PbO nanosized powder dispersed in water. Differentwaveforms were employed to determine the optimum size and shape of the drops. A uniform, defect-free pattern with dimensions of 4 mm × 4 mm can be printed using 20 V and a drop spacing of 20 μm. The inkjet-printed films were heated to 400 °C to remove the organics and subsequently sintered at 750 and 850 °C. The correlations between the density, grain size and electromechanical properties of the thick films and bulk ceramics are qualitatively discussed. A thickness coupling factor of 46% was obtained for a 15-μm-thick film sintered at low temperature of 850 °C, which is comparable to the value of the bulk ceramic with an identical nominal chemical composition. Our results are important for the economic and environmental-benign printing of piezoelectric materials applicable in variety of electronic devices, such as sensors, actuators, transformers, piezoelectric energy harvesters and transducers.
Technical Library | 2022-12-05 16:28:06.0
The work evaluates the impact of latent heat (LH) absorbed or released by a solder alloy during melting or solidification, respectively, on changes of dimensions of materials surrounding of the solder alloy. Our sample comprises a small printed circuit board (PCB) with a blind via filled with lead-free alloy SAC305. Differential scanning calorimetry (DSC) was employed to obtain the amount of LH per mass and a thermomechanical analyzer was used to measure the thermally induced deformation. A plateau during melting and a peak during solidification were detected during the course of dimension change. The peak height reached 1.6 μm in the place of the heat source and 0.3 μm in the distance of 3 mm from the source. The data measured during solidification was compared to a numerical model based on the finite element method. An excellent quantitative agreement was observed which confirms that the transient expansion of PCB during cooling can be explained by the release of LH from the solder alloy during solidification. Our results have important implications for the design of PCB assemblies where the contribution of recalescence to thermal stress can lead to solder joint failure.
Technical Library | 2019-09-04 21:35:53.0
Since the European Directives, RoHS (Restriction of Hazardous Substances) and REACH (Registration, Evaluation, Authorization and Restriction of Chemicals), entered into force in 2006-7, the number of regulated substances continues to grow. REACH adds new substances roughly twice a year, and more substances will be added to RoHS in 2019. While these open-ended regulations represent an ongoing burden for supply chain reporting, some ability to remain ahead of new substance restrictions can be achieved through full material declarations (FMD) specifically the IPC-1752A Class D Standard (the "Standard"), which was developed by the IPC - Association Connecting Electronic Industries. What is important to the supply chain is access to user-friendly, easily accessible or free, fully supported tools that allow suppliers to create and modify XML (Extensible Markup Language) files as specified in the Standard. Some tools will provide enhancements that validate required data entry and provide real-time interactive messages to facilitate the resolution of errors. In addition, validation and auto-population of substance CAS (Chemical Abstract Service) numbers, and Class D weight rollup validation ensure greater success in the acceptance of the declarations in customer systems that automate data gathering and reporting. A good tool should support importing existing IPC-1752A files for editing; this capability reduces the effort to update older declarations and greatly benefits suppliers of a family of products with similar composition. One of the problems with FMDs is the use of "wildcard" non-CAS numbers based on a declarable substance list (DSL). While the substances in different company's lists tend to have some overlap, no two DSL’s are the same. We provide an understanding of the commonality and differences between representative DSLs, and the ability to configure how much of a non-DSL substance percent is allowed. Case studies are discussed to show how supplier compliance data, can be automatically loaded into the customer's enterprise compliance system. Finally, we briefly discuss future enhancements and other developments like Once an Article, Always an Article (O5A) that will continue to require IPC standards and supporting tools to evolve.
Technical Library | 2019-08-07 22:56:45.0
The requirement to reconsider traditional soldering methods is becoming more relevant as the demand for bottom terminated components (QFN/BTC) increases. Thermal pads under said components are designed to enhance the thermal and electrical performance of the component and ultimately allow the component to run more efficiently. Additionally, low voiding is important in decreasing the current path of the circuit to maximize high speed and RF performances. The demand to develop smaller, more reliable, packages has seen voiding requirements decrease below 15 percent and in some instances, below 10 percent.Earlier work has demonstrated the use of micro-fluxed solder preforms as a mechanism to reduce voiding. The current work builds upon these results to focus on developing an engineered approach to void reduction in leadless components (QFN) through increasing understanding of how processing parameters and a use of custom designed micro-fluxed preforms interact. Leveraging the use of a micro-fluxed solder preform in conjunction with low voiding solder paste, stencil design, and application knowhow are critical factors in determining voiding in QFN packages. The study presented seeks to understand the vectors that can contribute to voiding such as PCB pad finish, reflow profile, reflow atmosphere, via configuration, and ultimately solder design.A collaboration between three companies consisting of solder materials supplier, a power semiconductor supplier, and an electronic assembly manufacturer worked together for an in-depth study into the effectiveness of solder preforms at reducing voiding under some of the most prevalent bottom terminated components packages. The effects of factors such as thermal pad size, finish on PCB, preform types, stencil design, reflow profile and atmosphere, have been evaluated using lead-free SAC305 low voiding solder paste and micro-fluxed preforms. Design and manufacturing rules developed from this work will be discussed.
