Technical Library | 2011-08-04 19:29:53.0
This work covers two major projects aimed at increasing quality and efficiency on a high mix, low volume surface mount electronics production line. Specifically the installation of a ten zone reflow oven and an enhanced changeover method for SMT pick and
Technical Library | 2015-01-08 17:26:59.0
Regardless of the accelerating trend for design and conversion to Pb-free manufacturing, many high reliability electronic equipment producers continue to manufacture and support tin-lead (SnPb) electronic products. Certain high reliability electronic products from the telecommunication, military, and medical sectors manufacture using SnPb solder assembly and remain in compliance with the RoHS Directive (restriction on certain hazardous substances) by invoking the European Union Pb-in-solder exemption. Sustaining SnPb manufacturing has become more challenging because the global component supply chain is converting rapidly to Pb-free offerings and has a decreasing motivation to continue producing SnPb product for the low-volume, high reliability end users. Availability of critical, larger SnPb BGA components is a growing concern
Technical Library | 2020-09-23 21:37:25.0
The need to minimise thermal damage to components and laminates, to reduce warpage-induced defects to BGA packages, and to save energy, is driving the electronics industry towards lower process temperatures. For soldering processes the only way that temperatures can be substantially reduced is by using solders with lower melting points. Because of constraints of toxicity, cost and performance, the number of alloys that can be used for electronics assembly is limited and the best prospects appear to be those based around the eutectic in the Bi-Sn system, which has a melting point of about 139°C. Experience so far indicates that such Bi-Sn alloys do not have the mechanical properties and microstructural stability necessary to deliver the reliability required for the mounting of BGA packages. Options for improving mechanical properties with alloying additions that do not also push the process temperature back over 200°C are limited. An alternative approach that maintains a low process temperature is to form a hybrid joint with a conventional solder ball reflowed with a Bi-Sn alloy paste. During reflow there is mixing of the ball and paste alloys but it has been found that to achieve the best reliability a proportion of the ball alloy has to be retained in the joint, particular in the part of the joint that is subjected to maximum shear stress in service, which is usually the area near the component side. The challenge is then to find a reproducible method for controlling the fraction of the joint thickness that remains as the original solder ball alloy. Empirical evidence indicates that for a particular combination of ball and paste alloys and reflow temperature the extent to which the ball alloy is consumed by mixing with the paste alloy is dependent on the volume of paste deposited on the pad. If this promising method of achieving lower process temperatures is to be implemented in mass production without compromising reliability it would be necessary to have a method of ensuring the optimum proportion of ball alloy left in the joint after reflow can be consistently maintained. In this paper the author explains how the volume of low melting point alloy paste that delivers the optimum proportion of retained ball alloy for a particular reflow temperature can be determined by reference to the phase diagrams of the ball and paste alloys. The example presented is based on the equilibrium phase diagram of the binary Bi-Sn system but the method could be applied to any combination of ball and paste alloys for which at least a partial phase diagram is available or could be easily determined.
Technical Library | 2022-10-31 17:30:40.0
This paper presents a quantitative analysis of solder joint reliability data for lead-free Sn-Ag-Cu (SAC) and mixed assembly (SnPb + SAC) circuit boards based on an extensive, but non-exhaustive, collection of thermal cycling test results. The assembled database covers life test results under multiple test conditions and for a variety of components: conventional SMT (LCCCs, resistors), Ball Grid Arrays, Chip Scale Packages (CSPs), wafer-level CSPs, and flip-chip assemblies with and without underfill. First-order life correlations are developed for SAC assemblies under thermal cycling conditions. The results of this analysis are put in perspective with the correlation of life test results for SnPb control assemblies. Fatigue life correlations show different slopes for SAC versus SnPb assemblies, suggesting opposite reliability trends under low or high stress conditions. The paper also presents an analysis of the effect of Pb contamination and board finish on lead-free solder joint reliability. Last, test data are presented to compare the life of mixed solder assemblies to that of standard SnPb assemblies for a wide variety of area-array components. The trend analysis compares the life of area-array assemblies with: 1) SAC balls and SAC or SnPb paste; 2) SnPb balls assembled with SAC or SnPb paste.
Technical Library | 2019-02-06 22:02:08.0
The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods, with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired, testing a variety of laminate materials (standard volume production with UL approval, low loss, and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified, as well as possible correlations or relationships among these higher speed test methods.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
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