Technical Library | 2019-06-21 10:39:15.0
Recently, an ACI Technologies (ACI) customer called to discuss failures that they had observed with some through-hole capacitor parts. The components were experiencing failures following vibration and accelerated stress testing. Upon receipt of the samples, ACI performed three levels of inspection and Energy Dispersive Spectroscopy (EDS) testing to investigate the root cause of the failures. These analyses enabled ACI to verify the elements comprising the solder joints and make the following recommendations in order to prevent future occurrences. The first inspection was to investigate the capacitor leads using optical microscopy, and no anomalies were found that could indicate bad parts from the vendor or improper handling prior to assembly. However, vertical fill in the barrel of the plated through-holes was too close to the IPC-A-610 minimum specification of 75% to determine a pass/fail condition, and therefore required further investigation.
Technical Library | 2019-06-06 00:19:02.0
More and more people and things are using electronic devices to communicate. Subsequently, many electronic products, in particular mobile base stations and core network nodes, need to handle enormous amounts of data per second. One important link in this communication chain is high speed pressfit connectors that are often used to connect mother boards and back planes in core network nodes. These new high speed pressfit connectors have several hundreds of thin, short and weak pins that are prone to damage. Small variations in via hole dimensions or hole plating thickness affect the connections; if the holes are too small, the pins may be bentor permanently deformed and if the holes are too large they will not form gas tight connections.The goal of this project was to understand how rework of these new high speed pressfit connectors affects connection strengths, hole wall deformations and plating cracks.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2015-12-23 16:57:27.0
The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.
Technical Library | 2020-03-12 13:10:35.0
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs.
Technical Library | 2007-06-06 15:25:30.0
Though today's microvias and high aspect plated through holes (PTH's) look nothing like the earliest through holes of 40 years ago, the PTH in its various forms remains the “weak link” and most critical element of printed wiring boards and laminate chip carriers (...) The paper outlines an approach to evaluating PTH reliability and quality that involves characterizing PTH life across a range of temperatures to reveal intricacies not seen by testing at a single delta-T, and certainly difficult to predict by modeling alone.
Technical Library | 2013-10-31 17:36:41.0
Multilayer printed circuit boards (PCBs) that utilize high performance materials are inherently far more challenging for a fabricator to build, due to significant material property differences over standard epoxy glass FR4. These unique material characteristics often require higher processing temperatures, special surface treatments (to aid in hole and surface plating), they possess different expansion properties, making layer-to-layer registration more difficult to control, and require many other unique considerations.
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
Technical Library | 2018-09-21 10:12:53.0
Moisture accumulates during storage and industry practice recommends specific levels of baking to avoid delamination. This paper will discuss the use of capacitance measurements to follow the absorption and desorption behaviour of moisture. The PCB design used in this work, focused on the issue of baking out moisture trapped between copper planes. The PCB was designed with different densities of plated through holes and drilled holes in external copper planes, with capacitance sensors located on the inner layers. For trapped volumes between copper planes, the distance between holes proved to be critical in affecting the desorption rate. For fully saturated PCBs, the desorption time at elevated temperatures was observed to be in the order of hundreds of hours. Finite difference diffusion modelling was carried out for moisture desorption behaviour for plated through holes and drilled holes in copper planes. A meshed copper plane was also modelled evaluating its effectiveness for assisting moisture removal and decreasing bake times. Results also showed, that in certain circumstances, regions of the PCB under copper planes initially increase in moisture during baking.
Technical Library | 2024-05-16 16:06:24.0
Much like actual cities where streets and roads connect buildings together, ICs on a board are connected to each other with copper traces. And just like any metropolitan city, urban expansion tends to move vertically instead of horizontally, but instead of multi-story buildings, we get multilayer boards. Vias are copper-plated holes spanning through the different layers of a given board or panel. They are the entrance locations to the subway stations, if you will. Having those multilayer boards has enabled electronic design to minimize the size of boards immensely without compromising on the complexity.
