Technical Library | 2023-01-10 20:15:42.0
Over the past years there has been consistent growth in the use of electroless nickel / immersion gold (ENIG) as a final finish. The finish is now frequently being used for PBGA, CSP, QFP and COB and more recently gathered considerable interest as a low cost under-bump metallization for flip chip bumping application. One of the largest users for this finish has been the telecommunication industry, were millions of square meters of PCBs with ENIG have been successfully used. The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via thermal integrity. In addition the nickel layer offers advantages such as co-planarity, Al-wire bondability and the use as contact surface for keypads or contact switching. Especially those pads, which are not covered by solder need a protective coating in corrosive environment – such as high humidity or pollutant gas.
Technical Library | 2023-11-14 19:24:08.0
In PCB circuit assemblies the trend is moving to more SMD components with finer pitch connections. The majority of the assemblies still have a small amount of through hole (THT) components. Some of them can't withstand high reflow temperatures, while others are there because of their mechanical robustness. In automotive applications these THT components are also present. Many products for cars, including steering units, radio and navigation, and air compressors also use THT technology to connect board-to-board, PCB's to metal shields or housings out of plastic or even aluminium. This is not a simple 2D plain soldering technology, as it requires handling, efficient thermal heating and handling of heavy (up to 10 kg) parts. Soldering technology becomes more 3D where connections have to be made on different levels. For this technology robots using solder wire fail because of the spattering of the flux in the wires and the long cycle time. In wave soldering using pallets the wave height is limited and pin in paste reflow is only a 2D application with space limitations.
Technical Library | 2013-01-24 19:16:35.0
The electronics industry has mainly adopted the higher melting point Sn3Ag0.5Cu solder alloys for lead-free reflow soldering applications. For applications where temperature sensitive components and boards are used this has created a need to develop low melting point lead-free alloy solder pastes. Tin-bismuth and tin-bismuth-silver containing alloys were used to address the temperature issue with development done on Sn58Bi, Sn57.6Bi0.4Ag, Sn57Bi1Ag lead-free solder alloy pastes. Investigations included paste printing studies, reflow and wetting analysis on different substrates and board surface finishes and head-in-pillow paste performance in addition to paste-in-hole reflow tests. Voiding was also investigated on tin-bismuth and tin-bismuth-silver versus Sn3Ag0.5Cu soldered QFN/MLF/BTC components. Mechanical bond strength testing was also done comparing Sn58Bi, Sn37Pb and Sn3Ag0.5Cu soldered components. The results of the work are reported.
Technical Library | 2016-11-30 15:53:15.0
The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
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