Technical Library | 2021-09-15 18:58:01.0
Mathematical model for dynamic force analysis of printed circuit boards has been designed to calculate dynamic deformations and stresses in printed circuit boards and assess their dynamic strength and rigidity. The represented model describes a printed circuit board as a separate oscillatory system, which is simulated as prismatic beam set on two oscillating supports. Simulation and assessment of stress and deflection in printed circuit boards and obtaining their amplitude frequency responses provided recommendations, which ensure strength and stiffness of printed circuit boards subjected to dynamic loads..
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
Technical Library | 2013-08-15 13:12:11.0
An automated visual PCB inspection is an approach used to counter difficulties occurred in human’s manual inspection that can eliminates subjective aspects and then provides fast, quantitative, and dimensional assessments. In this study, referential approach has been implemented on template and defective PCB images to detect numerous defects on bare PCBs before etching process, since etching usually contributes most destructive defects found on PCBs. The PCB inspection system is then improved by incorporating a geometrical image registration, minimum thresholding technique and median filtering in order to solve alignment and uneven illumination problem. Finally, defect classification operation is employed in order to identify the source for six types of defects namely, missing hole, pin hole, underetch, short-circuit, mousebite, and open-circuit.
Technical Library | 2007-11-01 17:16:07.0
This paper discusses micro-filled epoxy-based conducting adhesives modified with nanoparticles, conducting polymers, and low melting point (LMP) fillers for z-axis interconnections, especially as they relate to package level fabrication, integration,
Technical Library | 2013-10-24 15:47:53.0
Reflow soldering in a nitrogen atmosphere is a common process consideration in surface mount technology assembly. This is because the use of nitrogen in reflow equipment may benefit the process as well as the quality of the end product, where it can increase the reliability of the solder joint. (...) The present study investigated thoroughly the effect of different reflow soldering atmosphere, which is air and nitrogen on IMC formation and growth
Technical Library | 2020-10-18 19:31:27.0
Embedded components technology has launched its implementation in volume products demanding high levels of miniaturization. Small modules with embedded dies and passive components on the top side are mounted in hand held devices. Smartphones have been the enablers for this new technology using the capabilities of embedded components. With this technological background another business field became interesting for embedded components – the embedded power electronics. The roadmap of the automotive industry shows a clear demand for miniaturized power electronic applications. Drivers are the regulations for the international fleet emissions which are focusing on three major trends.
AT & S Austria Technologie & Systemtechnik Aktiengesellschaft
Technical Library | 2009-10-08 01:58:04.0
In the present study, we report novel ferroelectric-epoxy based polymer nanocomposites that have the potential to surpass conventional composites to produce thin film capacitors over large surface areas, having high capacitance density and low loss. Specifically, novel crack resistant and easy to handle Resin Coated Copper Capacitive (RC3) nanocomposites capable of providing bulk decoupling capacitance for a conventional power-power core, or for a three layer Voltage-Ground-Voltage type power core, is described.
Technical Library | 2014-05-29 13:48:14.0
Electronics packaging based on stress-engineered spring interconnects has the potential to enable integrated IC testing, fine pitch, and compliance not readily available with other technologies. We describe new spring contacts which simultaneously achieve low resistance ( 30 μm) in dense 2-D arrays (180 ~ 180-µm pitch). Mechanical characterization shows that individual springs operate at approximately 150-µN force. Electrical measurements and simulations imply that the interface contact resistance contribution to a single contact resistance is This paper suggests that integrated testing and packaging can be performed with the springs, enabling new capabilities for markets such as multichip modules.
Technical Library | 2022-01-05 23:10:11.0
Waste electrical and electronic equipment or e-waste generation has been skyrocketing over the last decades. This poses waste management and value recovery challenges, especially in developing countries. Printed circuit boards (PCBs) are mainly employed in value recovery operations. Despite the high energy costs of generating crushed and milled particles of the order of several microns, those are employed in conventional hydrometallurgical techniques. Coarse PCB pieces (of order a few centimetres) based value recovery operations are not reported at the industrial scale as the complexities of the internal structure of PCBs limit efficient metal and non-metal separation.
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