Technical Library | 2010-04-15 20:42:44.0
The high level of current interest in embedded passives in printed circuit boards is driven by the tremendous pressure to pack more circuitry into smaller spaces. However, adoption has been limited due to design, prototyping and infrastructure issues, as well as the stability and tolerances necessary for widespread replacement of discretes. The focus of this work has been to develop a polymer thick film resistor technology to incorporate reliable organic resistors inside printed wiring boards using standard PWB processing.
Technical Library | 2023-01-06 16:09:03.0
The 4-14 IPC Standards Committee recently created a revision to the IPC4552 specification for Electroless Nickel/Immersion Gold (ENIG) finished Printed Circuit Boards (PCB). Revision A brings a more comprehensive evaluation of metal layer thicknesses measurement, composition and introduces, for the first time, a quality aspect for nickel corrosion which has been historically connected to a defect called black line nickel or black pad.
Technical Library | 2024-04-29 21:39:52.0
In this paper, we develop and put into practice an Automatic Optical Inspection (AOI) system based on machine vision to check the holes on a printed circuit board (PCB). We incorporate the hardware and software. For the hardware part, we combine a PC, the three-axis positioning system, a lighting device and CCD cameras. For the software part, we utilize image registration, image segmentation, drill numbering, drill contrast, and defect displays to achieve this system. Results indicated that an accuracy of 5µm could be achieved in errors of the PCB holes allowing comparisons to be made. This is significant in inspecting the missing, the multi-hole and the incorrect location of the holes. However, previous work only focusses on one or other feature of the holes. Our research is able to assess multiple features: missing holes, incorrectly located holes and excessive holes. Equally, our results could be displayed as a bar chart and target plot. This has not been achieved before. These displays help users analyze the causes of errors and immediately correct the problems. Additionally, this AOI system is valuable for checking a large number of holes and finding out the defective ones on a PCB. Meanwhile, we apply a 0.1mm image resolution which is better than others used in industry. We set a detecting standard based on 2mm diameter of circles to diagnose the quality of the holes within 10 seconds.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2013-10-31 17:36:41.0
Multilayer printed circuit boards (PCBs) that utilize high performance materials are inherently far more challenging for a fabricator to build, due to significant material property differences over standard epoxy glass FR4. These unique material characteristics often require higher processing temperatures, special surface treatments (to aid in hole and surface plating), they possess different expansion properties, making layer-to-layer registration more difficult to control, and require many other unique considerations.
Technical Library | 2021-12-21 23:15:44.0
High Density Interconnect (HDI) technologies are being used widely in Asia and Europe in consumer electronics for portable wireless communication and computing, digital imaging, and chip packaging. Although North America lags behind in developing process capability for this technology, HDI will become a significant business segment for North America. For this to happen, the printed circuit board shops will have to become process capable in fabricating fine lines and spaces, and also be capable in forming and plating microvias.
Technical Library | 2013-03-07 18:25:36.0
The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2017-06-29 16:39:30.0
Currently there is no industry standard test method for measuring dielectric properties of circuit board materials at frequencies greater than about 10 GHz. Various materials vendors and test labs take different approaches to determine these properties. It is common for these different approaches to yield varying values of key properties like permittivity and loss tangent. The D-24C Task Group of IPC has developed this round robin program to assess these various methods from the "bottom up" to determine if standardized methods can be agreed upon to provide the industry with more accurate and valid characteristics of dielectrics used in high-frequency and high-speed applications.
Technical Library | 2013-08-08 15:23:11.0
In this project Machine Vision PCB Inspection System is applied at the first step of manufacturing, i.e., the making of bare PCB. We first compare a PCB standard image with a PCB image, using a simple subtraction algorithm that can highlight the main problem-regions. We have also seen the effect of noise in a PCB image that at what level this method is suitable to detect the faulty image. Our focus is to detect defects on printed circuit boards & to see the effect of noise. Typical defects that can be detected are over etchings (opens), under-etchings (shorts), holes etc...
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
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