Technical Library | 2001-04-24 10:41:53.0
Tau models describe the timing and functional information of component interfaces. Timing information specifies the delay in placing values on output signals and the timing constraints (set-up/hold, pulse-width) on input signals of a component. Functional information, through a finite state machine (FSM), specifies when output signal values change, when input signal values are latched, and how output values are determined as a function of input values.
Technical Library | 2012-12-14 14:28:20.0
This paper examines the potential failure mechanisms that can damage modern lowvoltage CMOS devices and their relationship to electrical testing. Failure mechanisms such as electrostatic discharge (ESD), CMOS latch-up, and transistor gate oxide degradation can occur as a result of electrical over-voltage stress (EOS). In this paper, EOS due to electrical testing is examined and an experiment is conducted using pulsed voltage waveforms corresponding to conditions encountered during in-circuit electrical testing. Experimental results indicate a correlation between amplitude and duration of the pulse waveform and device degradation due to one or more of the failure mechanisms.
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