Technical Library | 2012-12-17 22:05:22.0
Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.
Technical Library | 2020-04-14 15:49:38.0
The number of through-hole components on printed circuit boards (PCB) has declined significantly over the last decade. Miniaturization in electronics has resulted in less THT (through-hole technology) and leads with a finer pitch. For this reason, the soldering of these components has also changed from wave soldering to Point-to-point selective soldering. Soldering these small, fine-pitch components is a challenge when surface mount components (SMD) are positioned very close to THT components on the PCB layout. This study, done in cooperation with a large automotive EMS customer, defines the process windows for through-hole technology for fine-pitch components. It determines what is feasible to solder and defines layout design parameter that make soldering possible with SMD areas and other components on the assembly.
Technical Library | 2017-03-30 18:34:52.0
There are multiple methods, each with its associated benefits for given applications, for printing either solder paste or paste flux for BGA rework. Each of these methods is best-suited for a given situation, board layout and skill level of operators performing the BGA rework. This discussion will layout the various methods and present the specific circumstances for which the specific technique is most wellsuited. In addition, the pluses and minuses for each of the approaches will be discussed in detail.
Technical Library | 1999-05-06 14:19:44.0
In many high-performance VLSI designs, including all recent Intel microprocessors, datapath is implemented in a bit-sliced structure to simultaneously manipulate multiple bits of data. The circuit and layout of such structures are largely kept the same for each bit slice to achieve maximal performance, higher designer productivity, and better layout density. There are very few tools available to automate the design of a general datapath structure, most of which is done manually...
Technical Library | 1999-05-06 14:48:20.0
This paper describes manufacturing operations design and analysis at Intel. The complexities and forces of both the market and the manufacturing process combine to make the development of improved semiconductor fabrication manufacturing strategies (like lot dispatching, micro and macro scheduling policies, labor utilization, layout, etc.) particularly important...
Technical Library | 2001-04-24 10:44:24.0
This paper reviews the possible implementations of the Micro Via Technology within the Mentor Graphic's Board Station environment, specifically within the Librarian, Layout and Fablink applications. In this context, the definition of a Micro Via is constrained to Board Station’s support of such technology and contains only generalized descriptions of the manufacturing processes that require Micro Vias.
Technical Library | 2011-03-24 18:48:30.0
In this paper, a PCB layout technique is proposed to maintain ideal return paths for high-speed traces routing. Our goal is to implement and verify the digital LCD-TV in 2-layer PCB including the high-speed memory interfaces with less electromagnetic radi
Technical Library | 2024-02-05 17:51:01.0
Objective: Drying = reducing the humidity in PCB before soldering Preventing delamination caused by thermal stress after moisture absorption Methods: Drying in convection and/ or vacuum oven Parameters subject to material type, soldering surface, layer count, time to soldering, layout (copper-plated areas)
Technical Library | 2009-05-14 13:57:43.0
Is screen printing technology able to keep pace with rising quality demands and increasingly complex board layouts? Or, is new jet printing technology ready to fill the gap? A comparison study between the two methods reveals some interesting differences. Screen printers offer some possibilities for optimizing solder paste deposits, but optimization is far easier and quicker with the jet printer. At the same time, the ability to print individualized deposits on every single pcb pad may be the ultimate answer to the growing quality challenge.
Technical Library | 2018-02-01 00:31:48.0
This paper briefly summarizes the technologies underpinning the evolution in electrical system diagnosis and repair, which include schematic layout automation using prototypes and rule-based styling, instant language translation, 2D/3D view links with schematics, interactive diagnostic procedures, and dynamically-generated signal-tracing diagrams. These technologies empower after-sales service teams with state-of-the-art capabilities, which not only reduce costs but also improve brand quality in the eyes of its customers.
