Technical Library | 2020-12-10 15:49:40.0
Electronic assemblies should have longer and longer service life. Today there are partially demanded 20 years of functional capability for electronics for automotive application. On the other hand, smaller components, such as resistors of size 0201, are able to endure an increasing number of thermal cycles until fail of solder joints, so these are tested sometimes up to 4000 cycles. But testing until the end of life is essential for the determination of failure rates and the prognosis of reliability. Such tests require a lot of time, but this is often not available in developing of new modules. A further acceleration by higher cycle temperatures is usually not possible, because the materials are already operated at the upper limit of the load. However, the duration can be shortened by the use of liquids for passive tests, which allow faster temperature changes and shorter dwell times because of better heat transfer compared to air. The question is whether such tests lead to comparable results and what failure mechanisms are becoming effective. The same goes for active temperature cycles, in which the components itself are heated from inside and the substrate remains comparatively cold. This paper describes the various accelerated temperature cycling tests, compares and evaluates the related degradation of solder joints.
Technical Library | 2021-11-03 16:49:59.0
Ultrathin bare die chips were soldered using a novel soldering technology. Using homogeneous flash light generated by high-power xenon flash lamp the dummy components and the bare die NFC chips were successfully soldered to copper tracks on polyimide (PI) and polyethylene terephthalate (PET) flex foils by using industry standard Sn-Ag-Cu lead free alloys. Due to the selectivity of light absorption, a limited temperature increase was observed in the PET substrates while the chip and copper tracks were rapidly heated to a temperatures above the solder melting temperature. This allowed to successfully soldered components onto the delicate polyethylene foil substrates using lead-free alloys with liquidus temperatures above 200 °C. It was shown that by preheating components above the decomposition temperature of solder paste flux with a set of short low intensity pulses the processing window could be significantly extended compared to the process with direct illumination of chips with high intensity flash pulse. Furthermore, it was demonstrated that with localized tuning of pulse intensity components having different heat capacity could be simultaneously soldered using a single flash pulse.
Technical Library | 2021-11-17 18:53:50.0
The demand for product miniaturization, especially in the handheld device area, continues to challenge the board assembly industry. The desire to incorporate more functionality while making the product smaller continues to push board design to its limit. It is not uncommon to find boards with castle-like components right next to miniature components. This type of board poses a special challenge to the board assemblers as it requires a wide range of paste volume to satisfy both small and large components. One way to address the printing challenge is to use creative stencil design to meet the solder paste requirement for both large and small components. ... The most important attribute of a stencil is its release characteristic. In other words, how well the paste releases from the aperture. The paste release, in turn, depends on the surface characteristics of the aperture wall and stencil foil. The recent introduction of new technology, nano-coating for both stencil and squeegee blades, has drawn the attention of many researchers. As the name implies, nano-coated stencils and blades are made by a conventional method such as laser-cut or electroformed then coated with nano-functional material to alter the surface characteristics. This study will evaluate nano-coated stencils for passive component printing, including 01005.
Technical Library | 2022-09-12 14:07:47.0
Unique component handling issues can arise when an assembly factory uses highly-moisture sensitive surface mount devices (SMDs). This work describes how the distribution of moisture within the molded plastic body of a SMD is an important variable for survivability. JEDEC/IPC [1] moisture level rated packages classified as Levels 4-5a are shown to require additional handling constraints beyond the typical out-of-bag exposure time tracking. Nitrogen or desiccated cabinet containment is shown as a safe and effective means for long-term storage provided the effects of prior out-of-bag exposure conditions are taken into account. Moisture diffusion analyses coupled with experimental verification studies show that time in storage is as important a variable as floor-life exposure for highly-moisture sensitive devices. Improvements in floor-life survivability can be obtained by a handling procedure that includes cyclic storage in low humidity containment. SMDs that have exceeded their floor-life limits are analyzed for proper baking schedules. Optimized baking schedules can be adopted depending on a knowledge of the exposure conditions and the moisture sensitivity level of the device.
Technical Library | 2020-09-23 21:37:25.0
The need to minimise thermal damage to components and laminates, to reduce warpage-induced defects to BGA packages, and to save energy, is driving the electronics industry towards lower process temperatures. For soldering processes the only way that temperatures can be substantially reduced is by using solders with lower melting points. Because of constraints of toxicity, cost and performance, the number of alloys that can be used for electronics assembly is limited and the best prospects appear to be those based around the eutectic in the Bi-Sn system, which has a melting point of about 139°C. Experience so far indicates that such Bi-Sn alloys do not have the mechanical properties and microstructural stability necessary to deliver the reliability required for the mounting of BGA packages. Options for improving mechanical properties with alloying additions that do not also push the process temperature back over 200°C are limited. An alternative approach that maintains a low process temperature is to form a hybrid joint with a conventional solder ball reflowed with a Bi-Sn alloy paste. During reflow there is mixing of the ball and paste alloys but it has been found that to achieve the best reliability a proportion of the ball alloy has to be retained in the joint, particular in the part of the joint that is subjected to maximum shear stress in service, which is usually the area near the component side. The challenge is then to find a reproducible method for controlling the fraction of the joint thickness that remains as the original solder ball alloy. Empirical evidence indicates that for a particular combination of ball and paste alloys and reflow temperature the extent to which the ball alloy is consumed by mixing with the paste alloy is dependent on the volume of paste deposited on the pad. If this promising method of achieving lower process temperatures is to be implemented in mass production without compromising reliability it would be necessary to have a method of ensuring the optimum proportion of ball alloy left in the joint after reflow can be consistently maintained. In this paper the author explains how the volume of low melting point alloy paste that delivers the optimum proportion of retained ball alloy for a particular reflow temperature can be determined by reference to the phase diagrams of the ball and paste alloys. The example presented is based on the equilibrium phase diagram of the binary Bi-Sn system but the method could be applied to any combination of ball and paste alloys for which at least a partial phase diagram is available or could be easily determined.
Technical Library | 2008-02-20 21:42:52.0
Tier 2 and Tier 3 EMS companies face increasing pressure from competition in low-cost manufacturing countries to produce assembled boards at lower cost, with increased complexity and to tighter deadlines. They also face an increasing amount of high-mix, small-to-mediumvolume production runs. Even OEMs find it hard to predict what products they will be manufacturing in three to five years time, driving the need to invest in highly flexible production tools that will cater to their needs over the lifetime of the equipment. This paper examines methodologies for optimising the process, improving stock control and providing greater traceability using lean manufacturing techniques.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
Technical Library | 2019-09-11 23:33:04.0
There are numerous techniques to singulate printed circuit boards after assembly including break-out, routing, wheel cutting and now laser cutting. Lasers have several desirable advantages such as very narrow kerf widths as well as virtually no dust, no mechanical stress, visual pattern recognition and fast set-up changes. The very narrow kerf width resulting from laser ablation and the very tight tolerance of the cutting path placement allows for more usable space on the panel. However, the energy used in the laser cutting process can also create unwanted products on the cut walls as a result of the direct laser ablation. The question raised often is: What are these products, and how far can the creation of such products be mitigated through variation of the laser cutting process, laser parameters and material handling? This paper discusses the type and quantity of the products found on sidewalls of laser depaneled circuit boards and it quantifies the results through measurements of breakdown voltage, as well as electrical impedance. Further this paper discusses mitigation strategies to prevent or limit the amount of change in surface quality as a result of the laser cutting process. Depending on the final application of the circuit board it may prompt a need for proper specification of the expected results in terms of cut surface quality. This in turn will impact the placement of runs and components during layout. It will assist designers and engineers in defining these parameters sufficiently in order to have a predictable quality of the circuit boards after depaneling.
Technical Library | 2020-08-27 01:15:10.0
Automobile surface defects like scratches or dents occur during the process of manufacturing and cross-border transportation. This will affect consumers' first impression and the service life of the car itself. In most worldwide automobile industries, the inspection process is mainly performed by human vision, which is unstable and insufficient. The combination of artificial intelligence and the automobile industry shows promise nowadays. However, it is a challenge to inspect such defects in a computer system because of imbalanced illumination, specular highlight reflection, various reflection modes and limited defect features. This paper presents the design and implementation of a novel automatic inspection system (AIS) for automobile surface defects which are the located in or close to style lines, edges and handles. The system consists of image acquisition and image processing devices, operating in a closed environment and noncontact way with four LED light sources. Specifically, we use five plane-array Charge Coupled Device (CCD) cameras to collect images of the five sides of the automobile synchronously. Then the AIS extracts candidate defect regions from the vehicle body image by a multi-scale Hessian matrix fusion method. Finally, candidate defect regions are classified into pseudo-defects, dents and scratches by feature extraction (shape, size, statistics and divergence features) and a support vector machine algorithm. Experimental results demonstrate that automatic inspection system can effectively reduce false detection of pseudo-defects produced by image noise and achieve accuracies of 95.6% in dent defects and 97.1% in scratch defects, which is suitable for customs inspection of imported vehicles.
Technical Library | 2020-10-14 14:33:36.0
Epoxy based adhesives are prevalent interface materials for all levels of electronic packaging. One reason for their widespread success is their ability to accept fillers. Fillers allow the adhesive formulator to tailor the electrical and thermal properties of a given epoxy. Silver flake allow the adhesive to be both electrically conductive and thermally conductive. For potting applications, heat sinking, and general encapsulation where high electrical isolation is required, aluminum oxide has been the filler of choice. Today, advanced Boron Nitride filled epoxies challenge alternative thermal interface materials like silicones, greases, tapes, or pads. The paper discusses key attributes for designing and formulating advanced thermally conductive epoxies. Comparisons to other common fillers used in packaging are made. The filler size, shape and distribution, as well as concentration in the resin, will determine the adhesive viscosity and rheology. Correlation's between Thermal Resistance calculations and adhesive viscosity are made. Examples are shown that determination of thermal conductivity values in "bulk" form, do not translate into actual package thermal resistance. Four commercially available thermally conductive adhesives were obtained for the study. Adhesives were screened by shear strength measurements, Thermal Cycling ( -55 °C to 125 °C ) Resistance, and damp heat ( 85 °C / 85 %RH ) resistance. The results indicate that low modulus Boron Nitride filled epoxies are superior in formulation and design. Careful selection of stress relief agents, filler morphology, and concentration levels are critical choices the skilled formulator must make. The advantages and limitations of each are discussed and demonstrated.
