Technical Library | 2015-11-12 19:04:51.0
In order to provide the functionality in today’s electronics, printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces, this means no nodules, no pits, and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However, the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble, phosphorized, copper anodes introduce particulate and limits the ability to control plating distribution.
Technical Library | 2018-12-26 10:31:05.0
The development of novel interconnection materials for production of electronics is of considerable interest to fulfill increasing demands on interconnect reliability in increasingly demanding environments with respect to temperature extremes, mechanical stresses and/or production limitations. Adhesives are playing an increasingly significant role in the continuously evolving electronics industry. (...)Specific applications will be presented that highlight the feasibility of the technology with respect to conductivity, structural reliability and lifetime standards. The deposition of the novel ICA has been performed using a jet printing technology to ensure both precise and accurate positioning, size and volume delivery.
Technical Library | 2022-03-02 21:52:34.0
In today's consumer-driven electronic marketplace many products have a limited useful life and component suppliers are moving to shorter product lifecycles. However, there are several industries that require semiconductor components to have a much longer lifecycle. In many cases application lifecycles within the Industrial, Automotive, Medical, Aerospace and Defense sectors may extend up to 30 years or more. As a result, an ongoing component supply becomes critical to sustaining these applications throughout their useful lifecycle. For this reason, it is often a requirement that semiconductor components be stored for extended periods of time after production ends.
Technical Library | 2022-10-04 16:43:10.0
In this paper I will discuss the different methods and equipment used to detect counterfeit electronic parts, specifically integrated circuits as well as demonstrate some of the "red flags" that help to identify a part as being suspected counterfeit. We will begin with the initial receipt of the parts and the examination of the outer packaging, the basic visual inspection of the parts, the visual inspection and documentation at high magnification, permanency marking, blacktop test, scrape test, XRF (RoHS), decapsulation, X-ray, basic electrical testing, C-SAM, full function testing and limited function testing.
Technical Library | 1999-05-07 08:50:40.0
To enable transistor scaling into the 21st century, new solutions such as high dielectric constaConventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10mm in the 1970’s to a present day size of 0.1mm. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistorsnt materials for gate insulation and shallow, ultra low resistivity junctions need to be developed.
Technical Library | 2007-03-28 10:18:33.0
Legislation against the use of lead in electronics has been the driving force behind the use of lead-free solders, surface finishes, and component lead finishes. The major concern in using lead-free solders in the assembly and rework Chip Scale Packages (CSPs) is the relatively high temperatures that the components and the boards experience. Fine-pitch CSPs have very low standoff heights following assembly making inspection and rework of these components more difficult. One other concern pertinent to rework is the temperature of the neighboring components during rework. These issues, coupled with the limitations of rework equipment to handle lead-free reflow temperatures, make the task of reworking lead-free assemblies more challenging.
Technical Library | 2010-05-27 22:12:10.0
The quad flat pack no lead or quad flat non-leaded (QFN) is one of the fastest growing package types in the electronics industry today. While the advantages of QFNs are well documented, concerns arise with its reliability and manufacturability. Acceptance of this package, especially in long-life, severe-environment, high-reliability applications, is currently limited. One of the most common drivers for reliability failures is inappropriate adoption of new technologies, such as the case with QFN. In this presentation, we will review and discuss QFN related reliability concerns and challenges, and propose Physics-of-Failure (PoF) based approaches to allow the confident introduction of QFN components into electronics products.
Technical Library | 2010-06-24 21:20:05.0
Cost-effective assembly of custom-designed microelectromechanical systems (MEMS) for medium-caliber fuzes is challenging. In particular, the environment must have a setback acceleration exceeding 60,000g and centripetal acceleration of 9000g/mm out of center in a 30mm#2;173 projectile. In addition, the space available is very limited. The traditional approach is to mount the MEMS chip in a package that is then soldered to the printed circuit board (PCB). However, by mounting the MEMS chip directly to the PCB using conductive adhesive, we can increase the packaging density while reducing manufacturing cost.
Technical Library | 2013-03-07 18:25:36.0
The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2013-08-22 14:28:58.0
Tin-rich solders are widely applied in the electronic industry in the majority of modern printed circuit boards (PCBs). Because the use of lead-tin solders has been banned in the European Union since 2006, the problem of the bridging of adjacent conductors due to tin whisker growth (limited before by the addition of Pb) has been reborn. In this study tin alloys soldered on glass-epoxy laminate (typically used for PCBs) are considered. Scanning ion microscopy with Focused Ion Beam (FIB) system and energy-dispersive X-ray spectroscopy (EDXS) were used to determine correlations between spatial non-uniformities of the glass-epoxy laminate, the distribution of intermetallic compounds and whisker growth.
