Technical Library | 2020-01-01 17:06:52.0
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.
Technical Library | 2022-12-23 20:44:54.0
One of the upcoming reliability issues which is related to the lead-free solder introduction, are the headin-pillow solderability problems, mainly for BGA packages. These problems are due to excessive package warpage at reflow temperature. Both convex and concave warpage at reflow temperature can lead to the head-in-pillow problem where the solder paste and solder ball are in mechanical contact but not forming one uniform joint. With the thermo-Moiré profile measurements, this paper explains for two flex BGA packages the head-in-pillow. Both local and global height differences higher than 100 µm have been measured at solder reflow temperature. This can be sufficient to have no contact between the molten solder ball and solder paste. Finally, the impact of package drying is measured
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