Technical Library | 2023-01-17 17:12:33.0
Reflowed indium metal has for decades been the standard for solder thermal interface materials (solder TIMs or sTIMs) in most high-performance computing (HPC) TIM1 applications. The IEEE Heterogeneous Integration Thermal roadmap states that new thermal interface materials solutions must provide a path to the successful application of increased total-package die areas up to 100cm2. While GPU architectures are relatively isothermal during usage, CPU hotspots in complex heterogeneously-integrated modules will need to be able to handle heat flux hotspots up to 1000W/cm2 within the next two years. Indium and its alloys are used as reflowed solder thermal interface materials in both CPU and GPU "die to lid/heat spreader" (TIM1) applications. Their high bulk thermal conductivity and proven long-term reliability suit them well for extreme thermomechanical stresses. Voiding is the most important failure mode and has been studied by x-ray. The effects of surface pretreatment, pressure during reflow, solder flux type/fluxless processing, and preform design parameters, such as alloy type, are also examined. The paper includes data on both vacuum and pressure (autoclave) reflow of sTIMs, which is becoming necessary to meet upcoming requirements for ultralow voiding in some instances.
Technical Library | 2010-01-13 12:34:10.0
Micro-sectioning (sometimes referred to as cross-sectioning)is a technique, used to characterize materials or to perform a failure mode analysis, for exposing an internal section of a PCB or package. Destructive in nature, cross-sectioning requires encapsulation of the specimen in order to provide support, stability, and protection. Failures that can be investigated through micro-sectional analysis include component defects, thermo-mechanical failures, processing failures related to solder reflow, opens or shorts, voiding and raw material evaluations.
Technical Library | 2023-11-06 17:08:44.0
A new process has been developed for RF shielding on compact electronic communications devices using automated solder paste dispensing. The process is known as Shield Edge Interconnect (SEI). SEI designs enable parts to be processed though underfill before placing of the RF shield and allows more complete use of valuable PCB real estate to achieve reduced form factor requirements and/or for added components on products such as smartphones and tablets. The reduced form factor creates challenges for the assembly of those devices. This process, enabled by Speedline dispensing technology, relies on extremely accurate dispensing of solder paste on copper traces located along the outer edge of the PCB. The result is a robust process solution for SEI in which proprietary closed loop dispenser, pump, vision, and software technologies enable a high volume manufacturing (HVM) process.
Technical Library | 2016-11-17 14:58:02.0
Since 2006 RoHS requirements have required lead free solders to take the place of tin-lead solders in electronics. The problem is that in some environments the lead free solders are less reliable than the older tin-lead solders. One of the ways to solve this problem is to corner stake, edge bond or underfill the components. When considering what mitigation technique and material to use, the operating conditions must be characterized. The temperature range is important when selecting a material to use since the glass transition temperature (Tg) and coefficient of thermal expansion (CTE) are important properties. If improperly chosen, the mitigation material can cause more failures than an unmitigated component.
Technical Library | 2014-04-03 18:01:13.0
A system level modeling methodology is presented and validated on a simple case. It allows precise simulations of electrostatic discharge (ESD) stress propagation on a printed circuit board (PCB). The proposed model includes the integrated circuit (IC) ESD protection network, IC package, PCB lines, passives components, and externals elements. The impact of an external component on the ESD propagation paths into an IC is demonstrated. Resulting current and voltage waveforms are analyzed to highlight the interactions between all the elements of an operating PCB. A precise measurement technique was designed and used to compare with the simulation results. The model proposed in this paper is able to predict, with good accuracy, the propagation of currents and voltages into the whole system during ESD stress. It might be used to understand why failures occur and how to fix them with the most suitable solution.
Technical Library | 2022-12-19 18:59:51.0
Material and Process Characterization studies can be used to quantify the harmful effects that might arise from solder flux and other process residues left on external surfaces after soldering. Residues present on an electronic assembly can cause unwanted electrochemical reactions leading to intermittent performance and total failure. Components with terminations that extend underneath the package can trap flux residue. These bottom terminated components are flush with the bottom of the device and can have small solderable terminations located along the perimeter sides of the package. The clearance between power and ground render high electrical forces, which can propagate electrochemical interactions when exposed to atmospheric moisture (harsh environments). The purpose of this research is to predict and understand the functional performance of residues present under single row QFN component packages. The objective of the research study is to develop and collect a set of guidelines for understanding the relationship between ionic contamination and electrical performance of a BTC component when exposed to atmospheric moisture and the trade-offs between electrical, ionic contamination levels, and cleanliness. Utilizing the knowledge gained from undertaking the testing of QFN components and associated DOE, the team will establish a reference Test Suite and Test Spec for cleanliness.
Technical Library | 2015-07-16 17:24:23.0
Qualification of electronic hardware from a corrosion resistance standpoint has traditionally relied on stressing the hardware in a variety of environments. Before the development of tests based on mixed flowing gas (MFG), hardware was typically exposed to temperature-humidity cycling. In the pre-1980s era, component feature sizes were relatively large. Corrosion, while it did occur, did not in general degrade reliability. There were rare instances of the data center environments releasing corrosive gases and corroding hardware. One that got a lot of publicity was the corrosion by sulfur-bearing gases given off by data center carpeting. More often, corrosion was due to corrosive flux residues left on as-manufactured printed circuit boards (PCBs) that led to ion migration induced electrical shorting. Ion migration induced failures also occurred inside the PCBs due to poor laminate quality and moisture trapped in the laminate layers.
Technical Library | 2021-08-04 18:46:25.0
The process of printed circuit board assembly (PCBA) involves several machines, such as a stencil printer, placement machine and reflow oven, to solder and assemble electronic components onto printed circuit boards (PCBs). In the production flow, some failure prevention mechanisms are deployed to ensure the designated quality of PCBA, including solder paste inspection (SPI), automated optical inspection (AOI) and in-circuit testing (ICT). However, such methods to locate the failures are reactive in nature, which may create waste and require additional effort to be spent re-manufacturing and inspecting the PCBs. Worse still, the process performance of the assembly process cannot be guaranteed at a high level. Therefore, there is a need to improve the performance of the PCBA process. To address the aforementioned challenges in the PCBA process, an intelligent assembly process improvement system (IAPIS) is proposed, which integrates the k-means clustering method and multi-response Taguchi method to formulate a pro-active approach to investigate and manage the process performance.
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