Technical Library | 2023-01-17 17:37:45.0
Various international market trends drive electronics manufacturers and their mate- rials and equipment suppliers to develop new assembly techniques to reduce the industry's environmental impact. Two pri- mary forces in this drive are the movements to lead-free assembly and ISO 14000 cer- tification. In response to these factors, reflow technology advances are enabling manufacturers to meet or anticipate the new environmental mandates.
Technical Library | 2015-01-28 17:39:34.0
Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology.
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