Technical Library | 2024-08-16 22:29:20.0
Many engineers have a common frustration. Explaining the workings of some mechanism over a phone call or whilst sitting in a meeting without being hands-on with the product. Does the following sound familiar?
Technical Library | 2008-08-20 17:28:19.0
Kitting is the first step in printed circuit board assembly. It is initiated well in advance of the actual production start to be able to prepare and deliver the kit on time. Kitting involves the gathering of all the parts needed for a particular assembly from the stockroom and issuing the kit to the manufacturing line at the right time and in the right quantity. This paper discusses kitting, describes ways to eliminate waste in different phases of kitting, and illustrates lean kitting using a case study conducted in a major contract manufacturer site.
Technical Library | 2008-02-04 12:13:38.0
Engineers are always striving to make a lighter, faster and stronger PCB. In order to achieve their designs, engineers must turn to alternative materials to enhance their designs. There are many materials that allow for thermal, coefficient of thermal expansion (CTE) and rigidity. Many times if a material enables an engineer to have CTE they will have to sacrifice thermal. Currently carbon composite laminates are being used in order to achieve an ideal PCB with thermal, CTE and rigidity with almost no weight premiums.
Technical Library | 2022-05-02 21:35:53.0
Testing of electronic assemblies involves three elements: the device under test, test equipment, and fixturing to make the connections between them. The challenge for a test engineer building a sophisticated test system is that instrumentation may need to measure thousands of test points through the mechanical interconnect.
Technical Library | 2017-04-27 17:10:16.0
Using modern laser systems for the depanelization of circuit boards can create some challenges for the production engineer when it is compared to traditional mechanical singulation methods. Understanding the effects of the laser energy to the substrate material properly is essential in order to take advantage of the technology without creating unintended side effects. This paper presents an in-depth analysis of the various laser system operating parameters that were performed to determine the resulting substrate material temperature changes. A theoretical model was developed and compared to actual measurements. The investigation includes how the temperature increase resulting from laser energy during depaneling affects the properties of the PCB substrate, which varies from no measurable change to a lowering of the surface resistance of the cut wall depending on the cutting parameters.
Technical Library | 2020-06-10 01:42:55.0
Recent advancement of flexible wearable electronics allows significant enhancement of portable, continuous health monitoring and persistent human-machine interfaces. Enabled by flexible electronic systems, smart and connected bioelectronics are accelerating the integration of innovative information science and engineering strategies, ultimately driving the rapid transformation of healthcare and medicine. Recent progress in the development and engineering of soft materials has provided various opportunities to design different types of mechanically deformable systems towards smart and connected bioelectronics.
Technical Library | 2013-12-11 23:24:32.0
Today's analyses of electronics reliability at the system level typically use a "black box approach", with relatively poor understanding of the behaviors and performances of such "black boxes" and how they physically and electrically interact (...) The incorporation of more rigorous and more informative approaches and techniques needs to better understand (...) Understanding the Physics of Failure (PoF) is imperative. It is a formalized and structured approach to Failure Analysis/Forensics Engineering that focuses on total learning and not only fixing a particular current problem (...) In this paper we will present an explanation of various physical models that could be deployed through this method, namely, wire bond failures; thermo-mechanical fatigue; and vibration.
Technical Library | 2014-05-29 13:48:14.0
Electronics packaging based on stress-engineered spring interconnects has the potential to enable integrated IC testing, fine pitch, and compliance not readily available with other technologies. We describe new spring contacts which simultaneously achieve low resistance ( 30 μm) in dense 2-D arrays (180 ~ 180-µm pitch). Mechanical characterization shows that individual springs operate at approximately 150-µN force. Electrical measurements and simulations imply that the interface contact resistance contribution to a single contact resistance is This paper suggests that integrated testing and packaging can be performed with the springs, enabling new capabilities for markets such as multichip modules.
Technical Library | 2020-04-08 22:57:04.0
Flexible hybrid electronics (FHE), designed in wearable and implantable configurations, have enormous applications in advanced healthcare, rapid disease diagnostics, and persistent human-machine interfaces. Soft, contoured geometries and time-dynamic deformation of the targeted tissues require high flexibility and stretchability of the integrated bioelectronics. Recent progress in developing and engineering soft materials has provided a unique opportunity to design various types of mechanically compliant and deformable systems. Here, we summarize the required properties of soft materials and their characteristics for configuring sensing and substrate components in wearable and implantable devices and systems. Details of functionality and sensitivity of the recently developed FHE are discussed with the application areas in medicine, healthcare, and machine interactions. This review concludes with a discussion on limitations of current materials, key requirements for next generation materials, and new application areas.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
