Technical Library | 2001-04-24 10:44:24.0
This paper reviews the possible implementations of the Micro Via Technology within the Mentor Graphic's Board Station environment, specifically within the Librarian, Layout and Fablink applications. In this context, the definition of a Micro Via is constrained to Board Station’s support of such technology and contains only generalized descriptions of the manufacturing processes that require Micro Vias.
Technical Library | 2001-04-24 10:41:53.0
Tau models describe the timing and functional information of component interfaces. Timing information specifies the delay in placing values on output signals and the timing constraints (set-up/hold, pulse-width) on input signals of a component. Functional information, through a finite state machine (FSM), specifies when output signal values change, when input signal values are latched, and how output values are determined as a function of input values.
Technical Library | 2009-04-16 22:38:55.0
The worldwide electronics industry has sales of $750 billion, two thirds of which is accounted for by PCB assembly. PCB manufacturing is characterised by an obsessive drive for increased productivity in the context of three significant industry drivers: shorter product lifecycles, more complexity, outsourcing
Technical Library | 2012-04-19 21:50:46.0
Presented at IPC Apex 2012. Working through the New Product Introduction (NPI) flow between product design and manufacturing is usually a challenging process, with both parties being experts in their own fields and inextricably linked in the flow of g
Technical Library | 2001-04-24 10:38:38.0
Many PCB designers are interested in taking advantage of Multichip Modules, but are unfamiliar with the technology. While the design process is very much the same, MCM manufacturing processes vary dramatically. MCM routing requirements are dictated by the manufacturing process and types of components. Components mounted on MCM substrates are predominantly, if not exclusively, bare chips. As a result, the component body and I/O pins are no longer constrained to industry standard pin counts and form factors as are packaged components...
Technical Library | 2001-04-24 10:47:02.0
Board-level circuits today routinely run at speeds of 100 MHz or more and are composed of dozens of complex interacting VLSI components. To design such circuits in a timely and correct manner it is necessary to pay close attention to circuit timing early in the design cycle. At fast clock speeds, managing component and interconnect propagation delay becomes a key aspect of circuit design. It is imperative that the critical paths on a circuit and the slack available for interconnect delay consumption be identified early, and drive subsequent stages in the design flow.
Technical Library | 2016-06-30 14:00:32.0
When designing PLLs in nanometer CMOS, it is essential to validate the closed-loop PLL performance metrics with nanometer SPICE accuracy before going to silicon. Transistor-level, closed-loop PLL verification has been impractical due to traditional SPICE and RF simulator performance and capacity limitations. By using Analog FastSPICE, designers dont have to trade accuracy for performance. Read this white paper to see how AFS: Delivers closed-loop PLL transistor-level verification Supports direct jitter measurements Produces phase noise results correlating within 1-2dB of silicon
Technical Library | 2017-04-06 16:50:56.0
Silicon photonics is an IC technology where data is transferred using light that is routed on the chip using optical waveguides (Figure 1). Silicon photonics is best known as a method to solve problems with high input/output bandwidth applications. For example, because of ever-growing bandwidth requirements in datacenters, the optical transmit and receive heads are being placed closer and closer to the board and the IC. But, designers also apply this technology to biosensors, medical diagnostics, and environmental monitoring. Regardless of the application, photonic ICs always need integration to electronic circuits and this results in unique challenges.
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