Technical Library | 2022-10-11 20:15:14.0
The increased temperatures associated with Pb-free processes have produced significant challenges for PWB laminates. Newly developed laminates have different curing processes, are commonly filled with ceramic particles or micro-clays and can have higher Tg values. These changes which are aimed at improving the materials resistance to thermal excursions and maintaining electrical integrity through primary attach and rework operations have also had the effect of producing harder resin systems with lower fracture toughness.
Technical Library | 2001-04-24 10:44:24.0
This paper reviews the possible implementations of the Micro Via Technology within the Mentor Graphic's Board Station environment, specifically within the Librarian, Layout and Fablink applications. In this context, the definition of a Micro Via is constrained to Board Station’s support of such technology and contains only generalized descriptions of the manufacturing processes that require Micro Vias.
Technical Library | 1999-05-06 14:48:20.0
This paper describes manufacturing operations design and analysis at Intel. The complexities and forces of both the market and the manufacturing process combine to make the development of improved semiconductor fabrication manufacturing strategies (like lot dispatching, micro and macro scheduling policies, labor utilization, layout, etc.) particularly important...
Technical Library | 1999-05-06 11:18:25.0
The trend toward surface-mount assembly processes is making ball-grid array (BGA) packaging a popular choice for many types of devices, forcing designers to re-examine cooling of these large packages. While devices in BGAs transfer more heat to the board than leaded devices, the style of BGA packages has a large influence on the ability to transfer heat through other pathways, such as a top-mounted heat sink. Physical characteristics of the BGA further constrain the thermal designer. It takes forethought in board design to successfully accommodate devices that require significant heat dissipation. Multiple solutions exist, however, for BGA packages of all types.
Technical Library | 2015-03-04 10:56:26.0
As the proliferation of modern day electronics continues to drive miniaturization and functionality, electronic designers/assemblers face the issue of environmental exposure and uncommon applications never previously contemplated. This reality, coupled with the goal of reducing the environmental and health implications of the production and disposal of these devices, has forced manufacturers to reconsider the materials used in production. Furthermore, the need to increase package density and reduce costs has led to the rapid deployment of leadless packages such as QFN, POP, LGA, and Micro-BGA. In many cases, the manufacturers of these devices will recommend the use of no clean fluxes due to concerns over the ability to consistently remove flux residues from under and around these devices. These concerns, along with the need to implement a tin whisker mitigation strategy and/or increase environmental tolerance, have led to the conundrum of applying conformal coating over no clean residues.
Technical Library | 2013-01-09 18:31:54.0
The increased temperatures associated with lead free processes have produced significant challenges for PWB laminates. Newly developed laminates have different curing processes, are commonly filled with ceramic particles or micro-clays and can have higher Tg values. These changes designed to reduce Z-axis expansion and improve the materials resistance to thermal excursions through primary attach and rework operations have also produced harder resin systems with reduced fracture toughness.
Technical Library | 2021-05-06 13:45:49.0
The high-sensitive micro eddy-current testing (ECT) probe composed of planar meander coil as an exciter and spin-valve giant magneto-resistance (SV-GMR) sensor as a magnetic sensor for bare printed circuit board (PCB) inspection is proposed in this paper. The high-sensitive micro ECT probe detects the magnetic field distribution on the bare PCB and the image processing technique analyzes output signal achieved from the ECT probe to exhibit and to identify the defects occurred on the PCB conductor. The inspection results of the bare PCB model show that the proposed ECT probe with the image processing technique can be applied to bare PCB inspection. Furthermore, the signal variations are investigated to prove the possibility of applying the proposed ECT probe to inspect the high-density PCB that PCB conductor width and gap are less than 100 μm.
Technical Library | 2021-09-21 20:20:22.0
The electronics industry has been using the epoxy puck for the processing of the vast majority of electronics microsections since the 1970s. Minimal advancements have been seen in the methods used for precision micro-sections of PCBs, PCBAs, and device packages. This paper will discuss different techniques and approaches in performing precision and analytical micro-sections, which fuse the techniques and materials common in preparation of silicon wafers and bulk materials. These techniques have not only been found to produce excellent optical results, but transfer effectively to SEM for high magnification inspection and further analysis with minimal post-lapping preparation needed. Additionally, processing time is reduced primarily due to a significant reduction of bulk material removal earlier in the preparation, therefore needing less removal at later lapping steps compared to traditional sectioning methods. Additional techniques are introduced that mitigate some classic challenges experienced by technicians over the decades.
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2007-01-03 16:36:58.0
Solder paste dispensing is not a new process. However, today's microelectronics present a daunting array of technical challenges to meet deposit size requirements. The need for better paste formulations, more precise equipment, and more tightly controlled processes is driving paste suppliers and equipment suppliers to develop new methods and materials. The most challenging solder paste deposits are those smaller than 0.25mm in diameter and today’s electronics demand such deposits. This paper addresses the process requirements for solder paste micro-deposits in terms of material, equipment and process variable control required for success in producing 0.25mm and smaller deposits.
