Technical Library | 2014-08-07 15:13:44.0
Gold embrittlement in SnPb solder is a well-known failure mechanism in electronic assembly. To avoid this issue, prior studies have indicated a maximum gold content of three weight percent. This study attempts to provide similar guidance for Pb-free (SAC305) solder. Standard surface mount devices were assembled with SnPb and SAC305 solder onto printed boards with various thicknesses of gold plating. The gold plating included electroless nickel immersion gold (ENIG) and electrolytic gold of 15, 25, 35, and 50 microinches over nickel. These gold thicknesses resulted in weight percentages between 0.4 to 7.0 weight percent.
Technical Library | 2020-07-22 19:39:05.0
The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures. Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable. The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for a reliable PWB. Minimum copper wrap plating thickness has become an even a bigger concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design. PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching. The companies started a project to study the relationship between Copper wrap plating thickness and via reliability. The project had two phases. This paper will present findings from both Phase 1 and Phase 2.
Technical Library | 2021-04-21 19:28:30.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness.
Technical Library | 2014-11-06 16:43:24.0
This paper summarizes the results of recent investigations to examine the effect of electroless nickel process variations with respect to Pb-free (Sn-3.0Ag-0.5Cu) solder connections. These investigations included both ENIG and NiPd as surface finishes intended for second level interconnects in BGA applications. Process variations that are suspected to weaken solder joint reliability, including treatment time and pH, were used to achieve differences in nickel layer composition. Immersion gold deposits were also varied, but were directly dependent upon the plated nickel characteristics. In contrast to gold, different electroless palladium thicknesses were independently achieved by treatment time adjustments.
Technical Library | 2013-05-30 17:33:26.0
This paper covers the following topics: The Measurement Application, Measurement Requirements, Measurement Problems, Measurement Results, Reference Samples, Conclusions
Technical Library | 2023-01-06 16:09:03.0
The 4-14 IPC Standards Committee recently created a revision to the IPC4552 specification for Electroless Nickel/Immersion Gold (ENIG) finished Printed Circuit Boards (PCB). Revision A brings a more comprehensive evaluation of metal layer thicknesses measurement, composition and introduces, for the first time, a quality aspect for nickel corrosion which has been historically connected to a defect called black line nickel or black pad.
Technical Library | 2022-10-31 18:35:40.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness. Due to the various advantages they offer, the use of Ball Grid Array packages is common across all industry sectors. They are also prone to process voiding issues. This study was performed to determine if vacuum assisted reflow process can help alleviate the voids in area array solder joints. Test parameters in this study largely focused on vacuum pressure level and vacuum dwell time.
Technical Library | 2012-12-13 21:20:05.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4.
Technical Library | 2023-08-04 15:27:30.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2023-07-25 16:50:02.0
Some of the new handheld communication devices offer real challenges to the paste printing process. Normally, there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils. This paper will explore a different type of step stencil for this application; a "Two-Print Stencil Process" step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005, 0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil. Design guidelines for minimum keep-out distances between the relief step, the fine pitch apertures, and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.
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