Technical Library | 2012-08-16 22:38:05.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. The physical mechanisms behind tin whisker formation in pure tin (Sn) films continue to elude the microelectronics industry. Despite modest advances in whisker mitigation techniqu
Technical Library | 2021-08-11 01:00:37.0
Conformal coatings and potting materials continue to create issues for the electronics industry. This webinar will dig deeper into the failure modes of these materials, specifically issues with Coefficient of Thermal Expansion (CTE), delamination, cracking, de-wetting, pinholes/bubbles and orange peel issues with conformal coatings and what mitigation techniques are available. Similarly, this webinar will look at the failure modes of potting materials, (e.g Glass Transition Temperature (Tg), PCB warpage, the effects of improper curing and potential methods for correcting these situations.
Technical Library | 2016-11-17 14:58:02.0
Since 2006 RoHS requirements have required lead free solders to take the place of tin-lead solders in electronics. The problem is that in some environments the lead free solders are less reliable than the older tin-lead solders. One of the ways to solve this problem is to corner stake, edge bond or underfill the components. When considering what mitigation technique and material to use, the operating conditions must be characterized. The temperature range is important when selecting a material to use since the glass transition temperature (Tg) and coefficient of thermal expansion (CTE) are important properties. If improperly chosen, the mitigation material can cause more failures than an unmitigated component.
Technical Library | 2020-01-01 17:06:52.0
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.
Technical Library | 2021-09-21 20:20:22.0
The electronics industry has been using the epoxy puck for the processing of the vast majority of electronics microsections since the 1970s. Minimal advancements have been seen in the methods used for precision micro-sections of PCBs, PCBAs, and device packages. This paper will discuss different techniques and approaches in performing precision and analytical micro-sections, which fuse the techniques and materials common in preparation of silicon wafers and bulk materials. These techniques have not only been found to produce excellent optical results, but transfer effectively to SEM for high magnification inspection and further analysis with minimal post-lapping preparation needed. Additionally, processing time is reduced primarily due to a significant reduction of bulk material removal earlier in the preparation, therefore needing less removal at later lapping steps compared to traditional sectioning methods. Additional techniques are introduced that mitigate some classic challenges experienced by technicians over the decades.
Technical Library | 2019-09-11 23:33:04.0
There are numerous techniques to singulate printed circuit boards after assembly including break-out, routing, wheel cutting and now laser cutting. Lasers have several desirable advantages such as very narrow kerf widths as well as virtually no dust, no mechanical stress, visual pattern recognition and fast set-up changes. The very narrow kerf width resulting from laser ablation and the very tight tolerance of the cutting path placement allows for more usable space on the panel. However, the energy used in the laser cutting process can also create unwanted products on the cut walls as a result of the direct laser ablation. The question raised often is: What are these products, and how far can the creation of such products be mitigated through variation of the laser cutting process, laser parameters and material handling? This paper discusses the type and quantity of the products found on sidewalls of laser depaneled circuit boards and it quantifies the results through measurements of breakdown voltage, as well as electrical impedance. Further this paper discusses mitigation strategies to prevent or limit the amount of change in surface quality as a result of the laser cutting process. Depending on the final application of the circuit board it may prompt a need for proper specification of the expected results in terms of cut surface quality. This in turn will impact the placement of runs and components during layout. It will assist designers and engineers in defining these parameters sufficiently in order to have a predictable quality of the circuit boards after depaneling.
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