Technical Library | 2023-01-17 17:16:43.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Technical Library | 2023-05-22 17:46:29.0
Over the past several years, much research has been performed and published on the benefits of stencil nano-coatings and solvent under wipes. The process improvements are evident and well-documented in terms of higher print and end-of-line yields, in improved print volume repeatability, in extended under wipe intervals, and in photographs of the stencil's PCB-seating surface under both white and UV light. But quantifying the benefits using automated Solder Paste Inspection (SPI) methods has been elusive at best. SPI results using these process enhancements typically reveal slightly lower paste transfer efficiencies and less variation in print volumes to indicate crisper print definition. However, the improvements in volume data do not fully account for the overall improvements noted elsewhere in both research and in production.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2014-03-27 14:50:01.0
Because of the phase out of CFC's and HCFC's, standard solder pastes and fluxes evolved from RA and RMA fluxes, to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices.
Technical Library | 2022-02-16 15:34:32.0
Because of the phase-out of CFCs and HCFCs, standard solder pastes and fluxes evolved from RA and RMA fluxes to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices
Technical Library | 2023-05-22 16:49:42.0
Our customers' issues • Apertures are getting smaller • Paste does not release as well • Contaminates the bottom of the stencil • Increases defects / reduces yield Insufficient solder Bridging Solder balls on surface of PCB Flux residue • Requires more frequent cleaning • Reduced efficiency (wasted time) • Increased use of consumables (cost) USC fabric (use "cheap" fabric to reduce cost) Lint creates more defects Cleaning chemistries (use IPA to reduce cost) IPA breaks down flux and can create more defects
Technical Library | 2023-06-12 19:46:10.0
Solder paste printing is understood to be the leading contributor of defects in the electronics assembly process. Because yield accounts for such a large percentage of the margin, the greatest opportunity to improve profitability in the assembly of most electronics can be gained by reducing or eliminating solder defects. This article examines process adjustments made through stencil design that correct a misalignment situation between the PCB and stencil, leading to a 43% reduction in assembly defects. Examples of each are found in Table 1.
Technical Library | 2017-07-13 16:16:27.0
Controlled humidity and temperature controlled surface insulation resistance (SIR) measurements of flux covered test vehicles, subject to a direct current (D.C.) bias voltage are recognized by a number of global standards organizations as the preferred method to determine if no clean solder paste and wave soldering flux residues are suitable for reliable electronic assemblies. The IPC, Japanese Industry Standard (JIS), Deutsches Institut fur Normung (DIN) and International Electrical Commission (IEC) all have industry reviewed standards using similar variations of this measurement. (...) This study will compare the results from testing two solder pastes using the IPC-J-STD-004B, IPC TM-650 2.6.3.7 surface insulation resistance test, and IPC TM-650 2.3.25 in an attempt to investigate the correlation of ROSE methods as predictors of electronic assembly electrical reliability.
Technical Library | 2008-03-18 12:36:31.0
This paper examines the construction of a notebook mainboard with more than 2000 components and no wave soldering required. The board contains standard SMD, chipset BGAs, connectors, through hole components and odd forms placed using full automation and soldered after two reflow cycles under critical process parameters. However, state of the art technology does not help if the process parameters are not set carefully. Can all complex BGAs, THTs and even screws be soldered on a single stencil? What will help us overcome bridging, insufficient solder and thombstoning issues? This paper will demonstrate the placement of all odd shape components using pin-in-paste stencil design and full completion of the motherboard after two reflow cycles.
Technical Library | 2009-05-14 13:57:43.0
Is screen printing technology able to keep pace with rising quality demands and increasingly complex board layouts? Or, is new jet printing technology ready to fill the gap? A comparison study between the two methods reveals some interesting differences. Screen printers offer some possibilities for optimizing solder paste deposits, but optimization is far easier and quicker with the jet printer. At the same time, the ability to print individualized deposits on every single pcb pad may be the ultimate answer to the growing quality challenge.
