Technical Library | 2007-04-18 19:23:22.0
Recent investigations have revealed that Pb-free solder joints may be fragile, prone to premature interfacial failure particularly under shock loading, as initially formed or tend to become so under moderate thermal aging. Depending on the solder pad surface finish, different mechanisms are clearly involved, but none of the commonly used surface finishes appear to be consistently immune to embrittlement processes. This is of obvious concern for products facing relatively high operating temperatures for protracted times and/or mechanical shock or strong vibrations in service.
Technical Library | 2022-09-25 20:18:33.0
Printed circuit board (PCB) bending and/or flexing is an unavoidable phenomenon that is known to exist and is easily encountered during electronic board assembly processes. PCB bending and/or flexing is the fundamental source of tensile stress induced on the electronic components on the board assembly. For more brittle components, like ceramic-based electronic components, micro-cracks can be induced, which can eventually lead to a fatal failure of the components. For this reason, many standards organizations throughout the world specify the methods under which electronic board assemblies must be tested to ensure their robustness, sometimes as a pre-condition to more rigorous environmental tests such as thermal cycling or thermal shock.
Technical Library | 2007-05-09 18:26:16.0
High Density Interconnect (HDI) technology is fast becoming the enabling technology for the next generation of small portable electronic communication devices. These methods employ many different dielectrics and via fabrication technologies. In this research, the effect of the proximity of microvias to Plated Through Holes (PTHs) and its effect on the reliability of the microvias was extensively evaluated. The reliability of microvia interconnect structures was evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing (-55oC to +125oC). Comprehensive failure analysis was performed on microvias fabricated using different via fabrication technologies.
Technical Library | 2021-01-21 02:04:27.0
Traditional single level microvia structures are generally considered the most robust type of interconnection within a printed wire board (PWB) substrate. The rapid implementation of HDI technology now commonly requires between 2, 3 or 4 levels of microvias sequentially processed into the product. Recent OEM funded reliability testing has confirmed that by increasing the levels (stack height) these structures are proving less reliable, when compared to their single or double level counterparts. Recently false positive results have been recorded on products tested with traditional thermal shock testing methodology (cycling between -40°C and 125°C, or 145°C). A number of companies are incurring product failures resulting in increased costs associated with replacing the circuit boards, components and added labour.
Technical Library | 2021-09-15 19:00:35.0
This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a lifecycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.
Technical Library | 2015-02-12 16:57:56.0
Electronic systems are known to be affected by the environmental and mechanical conditions, such as humidity, temperature, thermal shocks and vibration. These adverse environmental operating conditions, with time, could degrade the mechanical efficiency of the system and might lead to catastrophic failures.The aim of this study is to investigate the mechanical integrity of lead-free ball grid array (BGA) solder joints subjected to isothermal ageing at 150°C for up to 1000 hours. Upon ageing at 150°C the Sn-3.5Ag solder alloy initially age-softened for up to 200 hours. This behaviour was linked to the coarsening of grains. When aged beyond 200 hours the shear strength was found to increase up to 400 hours. This age-hardening was correlated with precipitation of hard Ag3Sn particles in Sn matrix. Further ageing resulted in gradual decrease in shear strength. This can be explained as the combined effect of precipitation coarsening and growth of intermetallic layer. The fractured surfaces of the broken solder balls were also investigated under a Scanning Electron Microscope. The shear failures were generally due to ductile fractures in bulk solders irrespective of the ageing time.
Technical Library | 2015-12-31 15:19:28.0
Today's consumer electronic product are characterized by miniatuization, portability and light weight with high performance, especially for 3G mobile products. In the future more fine pitch CSPs (0.4mm) component will be required. However, the product reliability has been a big challenge with the fine pitch CSP. Firstly, the fine pitch CSPs are with smaller solder balls of 0.25mm diameter or even smaller. The small solder ball and pad size do weaken the solder connection and the adhesion of the pad and substrate, thus the pad will peel off easily from the PCB substrate. In addition, miniature solder joint reduce the strength during mechanical vibration, thermal shock, fatigue failure, etc. Secondly, applying sufficient solder paste evenly on the small pad of the CSP is difficult because stencil opening is only 0.25mm or less. This issue can be solved using the high end type of stencil such as Electroforming which will increase the cost.
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