Technical Library | 2011-01-20 19:50:30.0
This article introduces the technical development that went in to realizing an 80-layer ultra-multilayer printed circuit board, which meets the market demand for a "semiconductor test board supporting memory increases".
Technical Library | 2011-02-17 18:03:21.0
Copper ground pours are created by filling open unused areas with copper generally on the outer layers of the board then connecting the copper fill with stitching vias to ground. Usually, small isolated areas
Technical Library | 2008-10-29 18:45:53.0
Growing demand for compact, multi-function electronics products has accelerated component miniaturization and high-density placement, creating new challenges for the electronics manufacturing industry. It is no longer adequate to simply place parts accurately per a pre-defined CAD assembly program because solder paste alignment errors are increasing for numerous reasons. The solution to this problem is a system in which the placement machine can automatically detect and compensate for misalignment of the solder paste to produce high-quality boards regardless of the process errors beforehand.
Technical Library | 2013-04-25 11:42:01.0
Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2020-05-26 22:28:56.0
Both the number and the variants of Ball Grid Array packages (BGAs) are tending to increase on network Printed Board Assemblies (PBAs)with sizes ranging from a few mm die size Wafer Level Packages (WLPs) with low ball count up to large multi-die System-in-Package (SiP) BGAs with 60-70 mm side lengths and thousands of I/Os.
Technical Library | 2011-10-20 22:03:30.0
Results of FEM modelling of thermal stress analysis in printed circuit boards are given in the article. It is shown that thermal stress alone is not solely caused by differences in coefficients of thermal expansion of individual layers. The emergence of thermal stress is subject to both the layered structure of the wall and given boundary conditions, as well as the existence of a temperature gradient in the direction normal to the surface of the wall. A practical application focuses on the issue of recycling of PCB with the effort to achieve separation of layers due to thermal stress. Role modelling of thermal stress in this area lies in predicting the possibility of separation, depending on the type of thermal stress and material parameters.
Technical Library | 2013-10-31 17:36:41.0
Multilayer printed circuit boards (PCBs) that utilize high performance materials are inherently far more challenging for a fabricator to build, due to significant material property differences over standard epoxy glass FR4. These unique material characteristics often require higher processing temperatures, special surface treatments (to aid in hole and surface plating), they possess different expansion properties, making layer-to-layer registration more difficult to control, and require many other unique considerations.
Technical Library | 2019-11-07 08:59:14.0
Inductors realized with high permeable MnZn ferrite require, unlike iron-powder cores with an inherent dis-tributed gap, a discrete air gap in the magnetic circuit to prevent saturation of the core material and/or tune the inductance value. This large discrete gap can be divided into several partial gaps in order to reduce the air gap stray field and consequently the proximity losses in the winding. The multi-gap core, realized by stacking several thin ferrite plates and inserting a non-magnetic spacer material between the plates, however, exhibits a substan-tial increase in core losses which cannot be explained from the intrinsic properties of the ferrite. In this paper, a comprehensive overview of the scientific literature regarding machining induced core losses in ferrite, dating back to the early 1970s, is provided which suggests that the observed excess core losses could be attributed to a deterioration of ferrite properties in the surface layer of the plates caused by mechanical stress exerted during machining.
Technical Library | 2011-03-24 18:48:30.0
In this paper, a PCB layout technique is proposed to maintain ideal return paths for high-speed traces routing. Our goal is to implement and verify the digital LCD-TV in 2-layer PCB including the high-speed memory interfaces with less electromagnetic radi
Technical Library | 2021-12-21 23:21:34.0
Points of discussion in "HDI Microvia Technology – Cost Aspects" are: - Reasons for the use of HDI technology - Printed circuit board (PCB) size - Number of layers - Stack-up and complexity - Other important cost influences -–Design rules -–Drilling costs -–Microvia filling
