Technical Library | 2012-12-17 22:05:22.0
Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP, or any component for that matter, there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed, however, this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2019-10-03 14:27:01.0
Knowing how package warpage changes over temperature is a critical variable in order to assemble reliable surface mount attached technology. Component and component or component and board surfaces must stay relatively flat with one another or surface mount defects, such as head-in-pillow, open joints, bridged joints, stretched joints, etc. may occur. Initial package flatness can be affected by numerous aspects of the component manufacturing and design. However, change in shape over temperature is primarily driven by CTE mismatch between the different materials in the package. Thus material CTE is a critical factor in package design. When analyzing or modeling package warpage, one may assume that the package receives heat evenly on all sides, when in production this may not be the case. Thus, in order to understand how temperature uniformity can affect the warpage of a package, a case study of package warpage versus different heating spreads is performed.Packages used in the case study have larger form factors, so that the effect of non-uniformity can be more readily quantified within each package. Small and thin packages are less prone to issues with package temperature variation, due to the ability for the heat to conduct through the package material and make up for uneven sources of heat. Multiple packages and multiple package form factors are measured for warpage via a shadow moiré technique while being heated and cooled through reflow profiles matching real world production conditions. Heating of the package is adjusted to compare an evenly heated package to one that is heated unevenly and has poor temperature uniformity between package surfaces. The warpage is measured dynamically as the package is heated and cooled. Conclusions are drawn as to how the role of uneven temperature spread affects the package warpage.
Technical Library | 2013-08-01 13:17:44.0
Electronic industry uses a number of metallic materials in various forms. Also new materials and technology are introduced all the time for increased performance. In recent years, corrosion of electronic systems has been a significant issue. Multiplicity of materials used is one reason limiting the corrosion reliability. However, the reduced spacing between components on a printed circuit board (PCB) due to miniaturization of device is another factor that has made easy for interaction of components in corrosive environments. Presently the knowledge on corrosion issues of electronics is very limited. This paper reviews briefly the materials used in electronic systems, factors influencing corrosion, types of corrosion observed in electronics, and testing methods.
Technical Library | 2016-05-12 16:29:40.0
Advances in miniaturized electronic devices have led to the evolution of microvias in high density interconnect (HDI) circuit boards from single-level to stacked structures that intersect multiple HDI layers. Stacked microvias are usually filled with electroplated copper. Challenges for fabricating reliable microvias include creating strong interface between the base of the microvia and the target pad, and generating no voids in the electrodeposited copper structures. Interface delamination is the most common microvia failure due to inferior quality of electroless copper, while microvia fatigue life can be reduced by over 90% as a result of large voids, according to the authors’ finite element analysis and fatigue life prediction. This paper addresses the influence of voids on reliability of microvias, as well as the interface delamination issue.
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