Technical Library | 2019-01-10 10:24:47.0
We notice that the quantities of material that are to be dosed are becoming more and more divergent. In addition to large media volumes, small and very small quantities are also increasingly coming into focus. For example autonomous driving: These vehicles already produce an immense amount of data today. When potting the associated sensors, cameras, and ECUs, it is important to ensure a precise and repeatable media application – even with volumes of only 0.03 ml. In contrast, when high-voltage batteries for electric cars are potted, 5 to 10 litres of heat-conducting paste are required per vehicle – and the trend is rising. Optical bonding used in display production, on the other hand, is in the medium volume range. The challenge now is to cover the entire volume spectrum reliably and in compliance with the required cycle times. This is remedied by a modular system of scalable modules, which offers the customer the necessary flexibility and enables him to plan a system according to his needs.
Technical Library | 2021-11-03 16:36:36.0
Laser reflow soldering is an important technology in electronic components processing. In this paper, we presented a simple but efficient method to achieve reflow soldering process with gradient energy band created by just two parallel mirrors. The detailed influence of the variety of optical parameters on the soldering process has been analyzed by using the finite element method. And the modulation of the optical parameters on reflow soldering parameters also has been demonstrated. In our experiment, one HR mirror and one-mirror with transmissivity of 10% have been used to create a gradient energy band with an incident laser power of 50W. In summary, both the simulations and the experiments show that the typical reflow soldering profile has been acquired by the optical system. The high quality joints on both the front and rear surface of the capacitor can be acquired by just one surface radiation of the optical system.
Technical Library | 2014-11-28 15:55:13.0
A soldering alloy composition Sn40-Bi60 has been manufactured by quenching method to achieve the both cast and wire shape. Differential scanning calorimetric (DSC) was done to study the melting behavior for a large portion of the alloy melts sharply at a approximately 136 C0 ,the melting point of Sn-Bi. X-Ray diffraction and optical microscopy were used to analyzed its microstructure characterization. The hardness of the alloys has been tested and find at a value 2 HRB as ductile form.
Technical Library | 2024-04-29 21:39:52.0
In this paper, we develop and put into practice an Automatic Optical Inspection (AOI) system based on machine vision to check the holes on a printed circuit board (PCB). We incorporate the hardware and software. For the hardware part, we combine a PC, the three-axis positioning system, a lighting device and CCD cameras. For the software part, we utilize image registration, image segmentation, drill numbering, drill contrast, and defect displays to achieve this system. Results indicated that an accuracy of 5µm could be achieved in errors of the PCB holes allowing comparisons to be made. This is significant in inspecting the missing, the multi-hole and the incorrect location of the holes. However, previous work only focusses on one or other feature of the holes. Our research is able to assess multiple features: missing holes, incorrectly located holes and excessive holes. Equally, our results could be displayed as a bar chart and target plot. This has not been achieved before. These displays help users analyze the causes of errors and immediately correct the problems. Additionally, this AOI system is valuable for checking a large number of holes and finding out the defective ones on a PCB. Meanwhile, we apply a 0.1mm image resolution which is better than others used in industry. We set a detecting standard based on 2mm diameter of circles to diagnose the quality of the holes within 10 seconds.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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