Technical Library | 2020-12-24 02:50:56.0
A method for packaging integrated circuit silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm×8 mm× 0.53 mm and 2 mm×2 mm×0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three underfill adhesives (EP30AO, EP37-3FLF, and Epo-Tek 301 2fl), three highly flexible adhesives (Loctite 4860, Loctite 480, and Loctite 4902), and three substrates (Kapton,Mylar, and PEEK) have been evaluated, and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, was identified as the best materials combination with the optimum underfill and substrate thickness identified as 0.05 mm.
Technical Library | 2023-05-02 19:03:34.0
The demand for 0201 components in consumer products will increase sharply over the next few years due to the need for miniaturization. It is predicted that over 20 billion 0201 components will be used in more than one billion cell phones worldwide by the year 2003. Therefore, research and development on 0201 assembly is becoming a very hot topic. The first step to achieve a successful assembly process is to obtain a good PCB design for 0201 packages. This paper presents the data and criteria of PCB design for 0201 packages, including the pad design for 0201 components, and the minimum pad spacing or component clearance between 0201 components or between 0201 and other components. A systematic study on pad design and pad spacing was undertaken, using two test vehicles and three Design of Experiments (DOEs). In the first DOE, 2 out of 18 types of 0201 pad designs were selected based on process yield. The second DOE was focused on pad spacing, including 10mil, 8mil, 6mil and 4mil. The third experiment was final optimization, using two types of optimized pad designs with 10mil, 8mil and 6mil pad spacing. Through the above experiments, the design guideline for PCB layout for 0201 packages and the assembly process capability are identified.
Technical Library | 2018-03-21 22:44:30.0
Solder paste printing is the first step in the surface mount manufacturing process for PCBA assembly. When the solder paste printing process is uncontrolled, defects can be produced, which may not become apparent until the PCBA is downstream. (...)This paper will discuss how Lean Six Sigma techniques were used to optimize the solder paste printing process. It will highlight how a cross-functional team used the structured Define, Measure, Analyze, Improve and Control (DMAIC) methodology to identify and control the critical inputs. The advantage of the Lean Six Sigma methodology is that it guides the team through the rigorous structured process so that all possible inputs are considered and the critical ones can be identified.
Technical Library | 2024-05-31 19:29:15.0
A tight tolerance machine isn't necessarily a specific machine type. Rather, it's any machine capable of producing parts with precision tolerances. This means minimal variation in the final dimensions of the part. These cutting-edge tools are meticulously engineered to achieve exceptionally precise measurements within minuscule margins. This is accomplished with CNC, or computer numerical control, a manufacturing method that automates the movement of a machine and optimizes for precision. With technology and advanced techniques, these machines ensure that every component meets exact specifications, guaranteeing unparalleled accuracy in manufacturing processes.
Technical Library | 1999-05-07 11:35:19.0
Key competitive advantages can be obtained through the minimization of process defects and disruptions. In today's electronic manufacturing processes there are many variables to optimize. By gaining an understanding of what the defects are, and where they come from, is a key step in the process towards defect free/six sigma manufacturing. In the last decade, Surface Mount Technology processes have been slowly converting towards the No-Clean philosophy. This new trend has spawned new processing issues which need to be addressed. This paper will investigate solutions to current problems in the processing of No-Clean SMT processes.
Technical Library | 2013-04-04 15:28:39.0
This paper will outline and define what requirements must be adhered to for the OEM community to truly achieve the IPC class product from the Electrical Test standpoint. This will include the test point optimization matrix, Isolation (shorts) parameters and Continuity (opens) parameters. This paper will also address the IPC Class III/A additional requirements for Aerospace and Military Avionics. The disconnect exists between OEMs understanding the requirements of their specific IPC class design versus the signature that will be presented from their design. This results in many Class III builds failing at Electrical Test... First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2013-11-21 12:01:11.0
Previous experimentation on a highly miniaturized and densely populated SMT assembly revealed the optimum stencil alloy and flux-repellent coating for its stencil printing process. Production implementation of the materials that were identified in the study resulted in approximately 5% print yield improvement across all assemblies throughout the operation, validating the results of the initial tests. A new set of studies was launched to focus on the materials themselves, with the purpose of optimizing their performance on the assembly line (...) Results of the prior tests are reviewed, and the new test vehicle, experimental setup and results are presented and discussed.
Technical Library | 2015-12-14 13:40:04.0
A Manufacturing Execution System (MES) is a software program that manages and monitors production work in a factory. The MES controls and monitors all manufacturing data in real time, so there is no guesswork as to the status of any given job, machine, operator, etc. The focus is on short-interval scheduling (shift or day) with an emphasis on optimizing the distribution of work orders. Larger manufacturers have employed MES’s for years but many small to medium sized enterprises (SME’s) have yet to adopt such systems. The benefits of using an MES are many. Looking forward, I predict that even the smallest manufacturing companies will employ MES systems in the future.
Technical Library | 2017-06-13 13:28:22.0
The advent of miniaturized electronics for mobile phones and other portable devices has required the assembly of smaller and smaller components. Currently 01005 passives and 0.3 mm CSPs are some of the components that must be assembled to enable these portable electronic devices. It is widely accepted that about 65% of all end of the line defects occur in the stencil printing process. Given all of the above, it is critical that a precision stencil printing process be developed to support miniaturized electronic assembly.This paper is a summary of a significant amount of experimental data and process optimization techniques that were employed to establish a precision SMT printing process.
Technical Library | 2019-06-26 23:21:49.0
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating.
