Technical Library | 2023-08-02 18:18:23.0
As six sigma (6) and better processes are demanded for higher yields and as organizations move from measuring defects in terms of parts-per-million (ppm) towards parts-per-billion (ppb), the resolution of extant control charts is becoming insufficient to monitor process quality. This work describes the development of a new statistical process control (SPC) chart that is used to monitor processes in terms of defects-per-billion-opportunities (dpbo). A logical extension of the defects-per-million-opportunities (dpmo) control chart, calculations used to derive the dpbo control limits will be presented and examples of in-control and out-of-control processes will be offered.
Technical Library | 2017-06-15 00:44:19.0
Ceramics packages are being used in the electronics industry to operate the devices in harsh environments. In this paper we report a study on acoustic imaging technology for nondestructively inspecting underfill layers connecting organic interposers sandwiched between two ceramics substrates.First, we inspected the samples with transmission mode of scanning acoustic tomography (SAT) system, an inspection routine usually employed in assembly lines because of its simpler interpretation criteria: flawed region blocks the acoustic wave and appears darker. In this multilayer sample, this approach does not offer the crucial information at which layer of underfill has flaws. To resolve this issue, we use C-Mode Scanning in reflection mode to image layer by layer utilizing ultrasound frequencies from 15MHz to 120MHz. Although the sample is thick and contains at least 5 internal material interfaces, we are able to identify defective underfill layer interfaces.
Technical Library | 2014-12-11 18:00:09.0
The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Wire bonded packages using conventional copper lead frame have been used in industry for quite some time. However, the demand for consumer electronics is driving the need for flip chip interconnects as these packages shorten the signals, reduce inductance and improve functionality as compared to the wire bonded packages. The flip chip packages have solder bumps as interconnects instead of wire bonds and typically use an interposer or organic substrate instead of a metal lead frame (...) The paper provides a general overview of typical defects and failure modes seen in package assembly and reviews the efforts needed to understand new failure modes during package assembly. The root cause evaluations and lessons learned as the factory transitioned to thin form factor packages are shared
Technical Library | 2016-01-12 11:04:35.0
3D packaging has recently become very attractive because it can provide more flexibility in device design and supply chain, reduce the gap between silicon die and organic substrate, help miniaturize devices and meet the demand of high speed, provide more memory, more function and low cost. With the advancement of 3D packaging, the bump height is now down from 80μ to 10μ. When the bump diameter is 20-40μ and height 10μ, the process and reliability are obvious issues. It is well known that underfill can enhance the reliability for regular flip chip, however underfill won’t help assembly process. In order to resolve some difficulties that 3D packaging faces, YINCAE Advanced Materials, LLC has developed solderable anisotropic conductive adhesives for 3D package applications. In this paper we will discuss the assembly process and reliability in detail.
Technical Library | 2016-09-08 16:27:49.0
In this investigation a test matrix was completed utilizing 900 electrodes (small circuit board with parallel copper traces on FR-4 with LPI soldermask at 6, 10 and 50 mil spacing): 12 ionic contaminants were applied in five concentrations to three different spaced electrodes with five replicas each (three different bare copper trace spacing / five replications of each with five levels of ionic concentration). The investigation was to assess the electrical response under controlled heat and humidity conditions of the known applied contamination to electrodes, using the IPC SIR (surface insulation resistance) J-STD 001 limits and determine at what level of contamination and spacing the ionic / organic residue has a failing effect on SIR.
Technical Library | 2017-11-22 12:38:51.0
The use of copper foils laminated to polyimide (PI) as flexible printed circuit board precursor is a standard practice in the PCB industry. We have previously described[1] an approach to very thin copper laminates of coating uniform layers of nano copper inks and converting them into conductive foils via photonic sintering with a multibulb conveyor system, which is consistent with roll-to-roll manufacturing. The copper thickness of these foils can be augmented by electroplating. Very thin copper layers enable etching fine lines in the flexible circuit. These films must adhere tenaciously to the polyimide substrate.In this paper, we investigate the factors which improve and inhibit adhesion. It was found that the ink composition, photonic sintering conditions, substrate pretreatment, and the inclusion of layers (metal and organic) intermediate between the copper and the polyimide are important.
Technical Library | 2021-08-25 16:28:36.0
In this study, a Sn–Bi composite solder paste with thermosetting epoxy (TSEP Sn–Bi) was prepared by mixing Sn–Bi solder powder, flux, and epoxy system. The melting characteristics of the Sn–Bi solder alloy and the curing reaction of the epoxy system were measured by differential scanning calorimeter (DSC). A reflow profile was optimized based on the Sn–Bi reflow profile, and the Organic Solderability Preservative (OSP) Cu pad mounted 0603 chip resistor was chosen to reflow soldering and to prepare samples of the corresponding joint. The high temperature and humidity reliability of the solder joints at 85 #14;C/85% RH (Relative Humidity) for 1000 h and the thermal cycle reliability of the solder joints from
Technical Library | 2024-06-23 22:03:59.0
The melting temperatures of most lead-free solder alloys are somewhat higher than that of eutectic Sn/Pb solder, and many of the alloys tend to wet typical contact pads less readily. This tends to narrow down the fluxing and mass reflow process windows for assembly onto typical organic substrates and may enhance requirements on placement accuracy. Flip chip assembly here poses some unique challenges. The small dimensions provide for particular sensitivities to wetting and solder joint collapse, and underfilling does not reduce the demands on the intermetallic bond strength. Rather, the need to underfill lead to additional concerns in terms of underfill process control and reliability. Relatively little can here be learned from work on regular SMT components, BGAs or CSPs.
Technical Library | 2017-07-13 16:16:27.0
Controlled humidity and temperature controlled surface insulation resistance (SIR) measurements of flux covered test vehicles, subject to a direct current (D.C.) bias voltage are recognized by a number of global standards organizations as the preferred method to determine if no clean solder paste and wave soldering flux residues are suitable for reliable electronic assemblies. The IPC, Japanese Industry Standard (JIS), Deutsches Institut fur Normung (DIN) and International Electrical Commission (IEC) all have industry reviewed standards using similar variations of this measurement. (...) This study will compare the results from testing two solder pastes using the IPC-J-STD-004B, IPC TM-650 2.6.3.7 surface insulation resistance test, and IPC TM-650 2.3.25 in an attempt to investigate the correlation of ROSE methods as predictors of electronic assembly electrical reliability.
Technical Library | 2021-10-20 18:21:06.0
The solderability of the SAC305 alloy in contact with printed circuit boards (PCB) having different surface finishes was examined using the wetting balance method. The study was performed at a temperature of 260 _C on three types of PCBs covered with (1) hot air solder leveling (HASL LF), (2) electroless nickel immersion gold (ENIG), and (3) organic surface protectant (OSP), organic finish, all on Cu substrates and two types of fluxes (EF2202 and RF800). The results showed that the PCB substrate surface finish has a strong effect on the value of both the wetting time t0 and the contact angle h. The shortest wetting time was noted for the OSP finish (t0 = 0.6 s with EF2202 flux and t0 = 0.98 s with RF800 flux), while the ENIG finish showed the longest wetting time (t0 = 1.36 s with EF2202 flux and t0 = 1.55 s with RF800 flux). The h values calculated from the wetting balance tests were as follows: the lowest h of 45_ was formed on HASL LF (EF2202 flux), the highest h of 63_ was noted on the OSP finish, while on the ENIG finish, it was 58_ (EF2202 flux). After the solderability tests, the interface characterization of cross-sectional samples was performed by means of scanning electron microscopy coupled with energy dispersive spectroscopy.
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