Technical Library | 2007-02-01 10:08:40.0
The increased replacement of high lead count SMT devices with BGAs and other high ball count area array packages has brought increased challenges to PCB rework and repair. Often solder mask areas surrounding BGA pad areas are damaged when components are removed.
Technical Library | 2010-01-13 12:34:10.0
Micro-sectioning (sometimes referred to as cross-sectioning)is a technique, used to characterize materials or to perform a failure mode analysis, for exposing an internal section of a PCB or package. Destructive in nature, cross-sectioning requires encapsulation of the specimen in order to provide support, stability, and protection. Failures that can be investigated through micro-sectional analysis include component defects, thermo-mechanical failures, processing failures related to solder reflow, opens or shorts, voiding and raw material evaluations.
Technical Library | 2013-07-03 10:31:54.0
It has been demonstrated in numerous pieces of work that stencil printing, one of the most complex PCB assembly processes, is one of the largest contributors to defects (Revelino et el). This complexity extends to prototype builds where a small number of boards need to be assembled quickly and reliably. Stencil printing is becoming increasingly challenging as packages shrink in size, increase in lead count and require closer lead spacing (finer pitch). Prototype SMT assembly can be further divided between industrial and commercial work and the DIYer, hobbyist or researcher groups. This second group is highly price sensitive when it comes to the materials used for the board assembly as their funds are sourced from personal or research monies as opposed to company funds. This has led to development of a lower cost SMT printing stencil made from plastic film as opposed to the more traditional stainless steel stencil used by industrial and commercial users.This study compares the performance of these two traditional materials and their respective impact on solder paste printing including efficiency and print quality.
Technical Library | 2022-12-23 20:44:54.0
One of the upcoming reliability issues which is related to the lead-free solder introduction, are the headin-pillow solderability problems, mainly for BGA packages. These problems are due to excessive package warpage at reflow temperature. Both convex and concave warpage at reflow temperature can lead to the head-in-pillow problem where the solder paste and solder ball are in mechanical contact but not forming one uniform joint. With the thermo-Moiré profile measurements, this paper explains for two flex BGA packages the head-in-pillow. Both local and global height differences higher than 100 µm have been measured at solder reflow temperature. This can be sufficient to have no contact between the molten solder ball and solder paste. Finally, the impact of package drying is measured
Technical Library | 2016-05-30 22:24:00.0
As a part of series of studies on X-Ray inspection technology to quantify solder defects in BGA balls, we have conducted inspection of 3 level POP package by using a new AXI that capable of 3D-CT imaging. The new results are compared with the results of earlier AXI measurements. It is found that 3D measurements offer better defect inspection quality, lower false call and escapes.
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
Technical Library | 2013-12-19 16:57:50.0
With the adoption of RoHS and implementation of Lead Free solders a major concern is how this will impact reliability. Both commercial and military hardware are impacted by this change even though military hardware is considered exempt from the requirements of RoHS. As the supply chain has moved to the new lead free alloys both markets are being forced to understand these impacts and form risk mitigation strategies to deal with the change. This paper documents the effect of mixing Leaded and Lead Free alloys on BGA devices and how this impacts reliability. Three of the most common pitch BGA packages are included in the study to determine if the risk is the same as pitches decrease
Technical Library | 2012-10-18 21:58:51.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish.
Technical Library | 2019-10-03 14:27:01.0
Knowing how package warpage changes over temperature is a critical variable in order to assemble reliable surface mount attached technology. Component and component or component and board surfaces must stay relatively flat with one another or surface mount defects, such as head-in-pillow, open joints, bridged joints, stretched joints, etc. may occur. Initial package flatness can be affected by numerous aspects of the component manufacturing and design. However, change in shape over temperature is primarily driven by CTE mismatch between the different materials in the package. Thus material CTE is a critical factor in package design. When analyzing or modeling package warpage, one may assume that the package receives heat evenly on all sides, when in production this may not be the case. Thus, in order to understand how temperature uniformity can affect the warpage of a package, a case study of package warpage versus different heating spreads is performed.Packages used in the case study have larger form factors, so that the effect of non-uniformity can be more readily quantified within each package. Small and thin packages are less prone to issues with package temperature variation, due to the ability for the heat to conduct through the package material and make up for uneven sources of heat. Multiple packages and multiple package form factors are measured for warpage via a shadow moiré technique while being heated and cooled through reflow profiles matching real world production conditions. Heating of the package is adjusted to compare an evenly heated package to one that is heated unevenly and has poor temperature uniformity between package surfaces. The warpage is measured dynamically as the package is heated and cooled. Conclusions are drawn as to how the role of uneven temperature spread affects the package warpage.
Technical Library | 2014-12-11 18:00:09.0
The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Wire bonded packages using conventional copper lead frame have been used in industry for quite some time. However, the demand for consumer electronics is driving the need for flip chip interconnects as these packages shorten the signals, reduce inductance and improve functionality as compared to the wire bonded packages. The flip chip packages have solder bumps as interconnects instead of wire bonds and typically use an interposer or organic substrate instead of a metal lead frame (...) The paper provides a general overview of typical defects and failure modes seen in package assembly and reviews the efforts needed to understand new failure modes during package assembly. The root cause evaluations and lessons learned as the factory transitioned to thin form factor packages are shared
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