Technical Library | 2010-01-13 12:34:10.0
Micro-sectioning (sometimes referred to as cross-sectioning)is a technique, used to characterize materials or to perform a failure mode analysis, for exposing an internal section of a PCB or package. Destructive in nature, cross-sectioning requires encapsulation of the specimen in order to provide support, stability, and protection. Failures that can be investigated through micro-sectional analysis include component defects, thermo-mechanical failures, processing failures related to solder reflow, opens or shorts, voiding and raw material evaluations.
Technical Library | 2012-10-18 21:58:51.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish.
Technical Library | 2019-04-17 21:29:14.0
Electroless nickel electroless palladium immersion gold (ENEPIG) surface finish for printed circuit board (PCB) has now become a key surface finish that is used for both tin-lead and lead-free solder assemblies. This paper presents the reliability of land grid array (LGA) component packages with 1156 pads assembled with tin-lead solder onto PCBs with an ENEPIG finish and then subjected to thermal cycling and then isothermal aging.
Technical Library | 2014-08-19 15:39:13.0
Understanding warpage of package attach locations on PCBs under reflow temperature conditions is critical in surface mount technology. A new industry standard, IPC 9641, addresses this topic directly for the first time as an international standard.This paper begins by summarizing the sections of the IPC 9641 standard, including, measurement equipment selection, test setup and methodology, and accuracy verification. The paper goes further to discuss practical implementation of the IPC 9641 standards. Key advantages and disadvantages between available warpage measurement methods are highlighted. Choosing the correct measurement technique depends on requirements for warpage resolution, data density, measurement volume, and data correlation. From industry experience, best practice recommendations are made on warpage management of PCB land areas, covering how to setup, run, analyze, and report on local area PCB warpage.The release of IPC 9641 shows that flatness over temperature of the package land area on the PCB is critical to the SMT industry. Furthermore, compatibility of shapes between attaching surfaces in SMT, like a package and PCB, will be critical to product yield and quality in years to come.
Technical Library | 2021-09-21 20:20:22.0
The electronics industry has been using the epoxy puck for the processing of the vast majority of electronics microsections since the 1970s. Minimal advancements have been seen in the methods used for precision micro-sections of PCBs, PCBAs, and device packages. This paper will discuss different techniques and approaches in performing precision and analytical micro-sections, which fuse the techniques and materials common in preparation of silicon wafers and bulk materials. These techniques have not only been found to produce excellent optical results, but transfer effectively to SEM for high magnification inspection and further analysis with minimal post-lapping preparation needed. Additionally, processing time is reduced primarily due to a significant reduction of bulk material removal earlier in the preparation, therefore needing less removal at later lapping steps compared to traditional sectioning methods. Additional techniques are introduced that mitigate some classic challenges experienced by technicians over the decades.
Technical Library | 2021-09-15 19:00:35.0
This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a lifecycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems.
Technical Library | 2008-11-13 00:06:32.0
The electronics industry is facing issues with hot spots, solder joint stresses and Coefficient of Thermal Expansion (CTE) mismatch between PCB and IC substrate. Flip chip type packages for example have very low CTE compared to traditional PCB material. Thus it is necessary to have low CTE printed circuit boards in order to keep solder joint intact with such low CTE packages. There are currently several materials available in the market to address thermal and CTE challenges but each material has its own advantages and limitations...
Technical Library | 2022-02-21 19:49:16.0
The ability to undertake non-destructive testing on semiconductor devices, during both their manufacture and their subsequent use in printed circuit boards (PCBs), has become ever more important for checking product quality without compromising productivity. The use of x-ray inspection not only provides a potentially non-destructive test but also allows investigation within optically hidden areas, such as the wire bonding within packages and the quality of post solder reflow of area array devices (e.g. BGAs, CSPs and flip chips).
Technical Library | 2023-06-12 16:52:47.0
The technological advancement of component and PCB technology from through-hole to surface mount (SMT) is a major factor in the miniaturization of today's electronics. Smaller and smaller component sizes and more densely packed PCBs lead to more powerful designs in much smaller product packages. With advancement, however, comes a new set of challenges in building these smaller, more complex assemblies. This is the challenge original equipment manufacturers (OEM) and contract manufacturers (CM) face today.
Technical Library | 2014-11-13 19:23:50.0
With increasing power loss of electrical components, thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Due to the rapid advances in semiconductor technology, particularly in the regime of high-power components, the temperature dependence of the long-term reliability is a critical parameter and has to be considered with highest possible care during the design phase (...) The aim of this paper is to give a short overview about standard thermal solutions like thick copper, thermal vias, plugged vias or metal core based PCBs. Furthermore, attention will be turned on the development of copper filled thermal vias in thin board constructions...
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