Technical Library | 2007-08-02 13:24:23.0
This paper presents the results of a joint - three way study between Amkor Technology, Panasonic Factory Solutions and Spansion in the area of package on package (PoP) board level reliability (BLR) (...) The scope of this paper is to cover the already popular 14 x 14mm PoP package size that provides a 152 pin stacked interface which supports a high level of flexibility in the memory architecture for multimedia requirements.
Technical Library | 2018-11-06 12:42:25.0
Solder paste is a homogeneous, stable suspension of solder powder particles suspended in a flux binder, and is one of the most important process materials today in surface mount technology (SMT). By varying the solder particle size, distribution and shape, as well as the other constituent materials, the rheology and printing performance of solder pastes can be controlled. Paste flow behavior is very important in defining the printing performance of any paste.The purpose of this paper is to study the rheological behavior of SAC (Sn-Ag-Cu) solder paste used for surface mount applications in the electronic industry. The reason why the rheological tests are presented in this paper are two critical sub-processes: aperture filling and paste withdraw. In this paper, we report on the investigation of the rheological profiles, the serrated cone-to-plate system was found as effective in parameter minimizing the wall-slip effect
Technical Library | 2019-09-19 00:28:48.0
The symbiotic relationship between solder masks and selective finishes is not new. The soldermask application is one of the key considerations to ensure a successful application of a selective finish. The selective finish is the final chemical step of the PCB manufacturing process, this is when the panels are at their most valuable and are unfortunately not re-workable. Imperfections are not tolerated, even if they are wholly cosmetic. Quality issues often manifest themselves in the form of a 'ping pong' conversation between the fabricators, the soldermask suppliers and the selective finish suppliers. Without tangible evidence these discussions are difficult to resolve and the selective finish process is usually regarded as responsible. This paper will focus on the chemical characteristics and use them to predict or identify potential issues before they occur rather than specifically name 'critical' soldermasks. It is also the intention of this paper to address the potential of a soldermask to react to common yield hiking practices like UV bumping and oven curing. It is hoped that this awareness will help fabricators to ensure maximum yields by asking the right questions. 'Critical’ soldermasks impact all selective finishes. In this paper, practical experience using immersion tin will be used to highlight the relationship between 'critical' soldermasks and some of the issues seen in the field. The paper will include a novel approach to identify re-deposited volatiles after the reflow.
Technical Library | 1999-05-06 14:48:20.0
This paper describes manufacturing operations design and analysis at Intel. The complexities and forces of both the market and the manufacturing process combine to make the development of improved semiconductor fabrication manufacturing strategies (like lot dispatching, micro and macro scheduling policies, labor utilization, layout, etc.) particularly important...
Technical Library | 1999-05-06 14:03:04.0
This paper describes how Nikes innovative architecture addresses the expanding requirements of Intels next-generation processor designs while enabling a design environment that is more productive than one built with the previous tool generation.
Technical Library | 1999-05-07 10:16:31.0
This paper will describe practical aspects of a redundancy implementation on a high-volume cache memory product. Topics covered include various aspects of redundancy from a design and product engineering perspective; and present test development methods for future product implementations.
Technical Library | 1999-05-07 10:11:55.0
The Intel StrataFlashTM memory technology represents a cost breakthrough for flash memory devices by enabling the storage of two bits of data in a single flash memory transistor. This paper will discuss the evolution of the two bit/cell technology from conception to production.
Technical Library | 1999-05-07 10:13:38.0
This paper will review the device physics governing the operation of the industry standard ETOX™ flash memory cell and show how it is ideally suited for multiple bit per cell storage, through its storage of electrons on an electrically isolated floating gate and through its direct access to the memory cell.
Technical Library | 1999-05-07 10:47:00.0
White residue remaining after cleaning circuit board assemblies can be caused by a variety of chemicals and reactions. Rosin and water-soluble fluxes, circuit board resins and epoxies, component materials and other contamination all contribute to this complex chemistry. This paper discusses many of the sources of the residues that seem to be an ever-increasing occurrence.
Technical Library | 1999-05-09 13:07:16.0
This paper will give the reader a general understanding of EOS and ESD phenomena. It specifically addresses hand soldering's role in EOS and ESD and how to protect against and test for potential problems. It discusses how Metcal Systems address EOS and ESD concerns and how they differ from conventional soldering systems.
