Technical Library | 2021-08-25 16:28:36.0
In this study, a Sn–Bi composite solder paste with thermosetting epoxy (TSEP Sn–Bi) was prepared by mixing Sn–Bi solder powder, flux, and epoxy system. The melting characteristics of the Sn–Bi solder alloy and the curing reaction of the epoxy system were measured by differential scanning calorimeter (DSC). A reflow profile was optimized based on the Sn–Bi reflow profile, and the Organic Solderability Preservative (OSP) Cu pad mounted 0603 chip resistor was chosen to reflow soldering and to prepare samples of the corresponding joint. The high temperature and humidity reliability of the solder joints at 85 #14;C/85% RH (Relative Humidity) for 1000 h and the thermal cycle reliability of the solder joints from
Technical Library | 2023-06-12 18:33:29.0
This paper presents a real-time predictive approach to improve solder paste stencil printing cycle decision making process in surface mount assembly lines. Stencil cleaning is a critical process that influences the quality and efficiency of printing circuit board. Stencil cleaning operation depends on various process variables, such as printing speed, printing pressure, and aperture shape. The objective of this research is to help efficiently decide stencil printing cleaning cycle by applying data-driven predictive methods. To predict the printed circuit board quality level, a recurrent neural network (RNN) is applied to obtain the printing performance for the different cleaning aging. In the prediction model, not only the previous printing performance statuses are included, but also the printing settings are used to enhance the RNN learning. The model is tested using data collected from an actual solder paste stencil printing line. Based on the predicted printing performance level, the model can help automatically identify the possible cleaning cycle in practice. The results indicate that the proposed model architecture can predictively provide accurate solder paste printing process information to decision makers and increase the quality of the stencil printing process.
Technical Library | 2013-02-08 22:56:47.0
Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.
Technical Library | 2014-03-27 14:50:01.0
Because of the phase out of CFC's and HCFC's, standard solder pastes and fluxes evolved from RA and RMA fluxes, to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices.
Technical Library | 2022-02-16 15:34:32.0
Because of the phase-out of CFCs and HCFCs, standard solder pastes and fluxes evolved from RA and RMA fluxes to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices
Technical Library | 2023-06-12 19:46:10.0
Solder paste printing is understood to be the leading contributor of defects in the electronics assembly process. Because yield accounts for such a large percentage of the margin, the greatest opportunity to improve profitability in the assembly of most electronics can be gained by reducing or eliminating solder defects. This article examines process adjustments made through stencil design that correct a misalignment situation between the PCB and stencil, leading to a 43% reduction in assembly defects. Examples of each are found in Table 1.
Technical Library | 2018-06-13 11:42:00.0
The art of screen printing solder paste for the surface mount community has been discussed and presented for several decades. However, the impending introduction of passive Metric 0201 devices has reopened the need to re-evaluate the printing process and the influence of stencil architecture. The impact of introducing apertures with architectural dimensions’ sub 150um whilst accommodating the requirements of the standard suite of surface mount connectors, passives and integrated circuits will require a greater knowledge of the solder paste printing process.The dilemma of including the next generation of surface mount devices into this new heterogeneous environment will create area ratio challenges that fall below todays 0.5 threshold. Within this paper the issues of printing challenging area ratio and their associated aspect ratio will be investigated. The findings will be considered against the next generation of surface mount devices.
Technical Library | 2023-11-06 17:08:44.0
A new process has been developed for RF shielding on compact electronic communications devices using automated solder paste dispensing. The process is known as Shield Edge Interconnect (SEI). SEI designs enable parts to be processed though underfill before placing of the RF shield and allows more complete use of valuable PCB real estate to achieve reduced form factor requirements and/or for added components on products such as smartphones and tablets. The reduced form factor creates challenges for the assembly of those devices. This process, enabled by Speedline dispensing technology, relies on extremely accurate dispensing of solder paste on copper traces located along the outer edge of the PCB. The result is a robust process solution for SEI in which proprietary closed loop dispenser, pump, vision, and software technologies enable a high volume manufacturing (HVM) process.
Technical Library | 2019-05-22 21:24:05.0
voidless treatment Smaller components -> miniaturization (01005 capability) Large board handling -> dynamic preheating for large board repair Repeatable processes -> flux and paste application (Dip and Print), residual solder removal (scavenging), dispensing, multiple component handling, and traceability Operator support -> higher automation, software guidance
Technical Library | 2023-05-22 17:46:29.0
Over the past several years, much research has been performed and published on the benefits of stencil nano-coatings and solvent under wipes. The process improvements are evident and well-documented in terms of higher print and end-of-line yields, in improved print volume repeatability, in extended under wipe intervals, and in photographs of the stencil's PCB-seating surface under both white and UV light. But quantifying the benefits using automated Solder Paste Inspection (SPI) methods has been elusive at best. SPI results using these process enhancements typically reveal slightly lower paste transfer efficiencies and less variation in print volumes to indicate crisper print definition. However, the improvements in volume data do not fully account for the overall improvements noted elsewhere in both research and in production.
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