Technical Library | 2023-01-17 17:19:44.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Technical Library | 2021-04-21 19:28:30.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness.
Technical Library | 2018-02-28 22:28:30.0
Circuit functional density requirements continue to drive innovative approaches to high performance packaging. Some new approaches include; aggressive space reduction, embedded solutions, and those that offer some form of risk reduction and rework potential are now options that are being explored by customers. Requirements for assembly of these types of packages necessitate the deposition of solder paste and assembly of components into cavities of the substrates to gain z-axis density as well as area functional density. Advances in the fabrication of PWB’s with cavities using newly developed laser micro-fabrication processes along with increased circuit pitch density of 50 micron lines and spaces permit new applications for high performance electronic substrates. First published at SMTA Pan Pacific Symposium
Technical Library | 2023-06-12 19:46:10.0
Solder paste printing is understood to be the leading contributor of defects in the electronics assembly process. Because yield accounts for such a large percentage of the margin, the greatest opportunity to improve profitability in the assembly of most electronics can be gained by reducing or eliminating solder defects. This article examines process adjustments made through stencil design that correct a misalignment situation between the PCB and stencil, leading to a 43% reduction in assembly defects. Examples of each are found in Table 1.
Technical Library | 2018-10-03 20:41:44.0
Voids in solder joints plague many electronics manufacturers. Do you have voids in your life? We have good news for you, there are many excellent ways to "Fill the Void." This paper is a continuation of previous work on voiding in which the following variables were studied: water soluble lead-free solder pastes, a variety of stencil designs, and reflow profiles. Quad Flat No-Lead (QFN) component thermal pads were used as the test vehicle. The voiding results were summarized and recommendations were made for reduction of voiding.
Technical Library | 2018-07-18 16:28:26.0
Reduction of first pass defects in the SMT assembly process minimizes cost, assembly time and improves reliability. These three areas, cost, delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process. It is commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process. As form factor continues to get smaller, the challenge to obtain 100% yield becomes more difficult.This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause. Outer layer copper weight and surface treatment will also be addressed as to their effect on printability. Experiments using leadless and emerging components will be studied and root cause analysis will be presented
Technical Library | 2020-11-24 23:01:04.0
The miniaturization trend is driving industry to adopting low standoff components or components in cavity. The cost reduction pressure is pushing telecommunication industry to combine assembly of components and electromagnetic shield in one single reflow process. As a result, the flux outgassing/drying is getting very difficult for devices due to poor venting channel. This resulted in insufficiently dried/burnt-off flux residue. For a properly formulated flux, the remaining flux activity posed no issue in a dried flux residue for no-clean process. However, when venting channel is blocked, not only solvents remain, but also activators could not be burnt off. The presence of solvents allows mobility of active ingredients and the associated corrosion, thus poses a major threat to the reliability. In this work, a new halogen-free no-clean SnAgCu solder paste, 33-76-1, has been developed. This solder paste exhibited SIR value above the IPC spec 100 MΩ without any dendrite formation, even with a wet flux residue on the comb pattern. The wet flux residue was caused by covering the comb pattern with 10 mm × 10 mm glass slide during reflow and SIR testing in order to mimic the poorly vented low standoff components. The paste 33-76-1 also showed very good SMT assembly performance, including voiding of QFN and HIP resistance. The wetting ability of paste 33-76-1 was very good under nitrogen. For air reflow, 33-76-1 still matched paste C which is widely accepted by industry for air reflow process. The above good performance on both non-corrosivity with wet flux residue and robust SMT process can only be accomplished through a breakthrough in flux technology.
Technical Library | 2019-08-07 22:56:45.0
The requirement to reconsider traditional soldering methods is becoming more relevant as the demand for bottom terminated components (QFN/BTC) increases. Thermal pads under said components are designed to enhance the thermal and electrical performance of the component and ultimately allow the component to run more efficiently. Additionally, low voiding is important in decreasing the current path of the circuit to maximize high speed and RF performances. The demand to develop smaller, more reliable, packages has seen voiding requirements decrease below 15 percent and in some instances, below 10 percent.Earlier work has demonstrated the use of micro-fluxed solder preforms as a mechanism to reduce voiding. The current work builds upon these results to focus on developing an engineered approach to void reduction in leadless components (QFN) through increasing understanding of how processing parameters and a use of custom designed micro-fluxed preforms interact. Leveraging the use of a micro-fluxed solder preform in conjunction with low voiding solder paste, stencil design, and application knowhow are critical factors in determining voiding in QFN packages. The study presented seeks to understand the vectors that can contribute to voiding such as PCB pad finish, reflow profile, reflow atmosphere, via configuration, and ultimately solder design.A collaboration between three companies consisting of solder materials supplier, a power semiconductor supplier, and an electronic assembly manufacturer worked together for an in-depth study into the effectiveness of solder preforms at reducing voiding under some of the most prevalent bottom terminated components packages. The effects of factors such as thermal pad size, finish on PCB, preform types, stencil design, reflow profile and atmosphere, have been evaluated using lead-free SAC305 low voiding solder paste and micro-fluxed preforms. Design and manufacturing rules developed from this work will be discussed.
Technical Library | 2022-10-31 17:09:04.0
The global transition to lead-free (Pb-free) electronics has led component and equipment manufacturers to transform their tin–lead (SnPb) processes to Pb-free. At the same time, Pb-free legislation has granted exemptions for some products whose applications require high long-term reliability. However, due to a reduction in the availability of SnPb components, compatibility concerns can arise if Pb-free components have to be utilized in a SnPb assembly. This compatibility situation of attaching a Pb-free component in a SnPb assembly is generally termed "backward compatibility." This paper presents the results of microstructural analysis of mixed solder joints which are formed by attaching Pb-free solder balls (SnAgCu) of a ball-grid-array component using SnPb paste. The experiment evaluates the Pb phase coarsening in bulk solder microstructure and the study of intermetallic compounds formed at the interface between the solder and the copper pad.
Technical Library | 2018-09-26 20:33:26.0
Bottom terminated components, or BTCs, have been rapidly incorporated into PCB designs because of their low cost, small footprint and overall reliability. The combination of leadless terminations with underside ground/thermal pads have presented a multitude of challenges to PCB assemblers, including tilting, poor solder fillet formation, difficult inspection and – most notably – center pad voiding. Voids in large SMT solder joints can be difficult to predict and control due to the variety of input variables that can influence their formation. Solder paste chemistries, PCB final finishes, and reflow profiles and atmospheres have all been scrutinized, and their effects well documented. Additionally, many of the published center pad voiding studies have focused on optimizing center pad footprint and stencil aperture designs. This study focuses on I/O pad stencil modifications rather than center pad modifications. It shows a no-cost, easily implemented I/O design guideline that can be deployed to consistently and repeatedly reduce void formation on BTC-style packages.
| 1 |
