Technical Library | 2010-09-16 18:45:06.0
With PCB complexity and density increasing and also wider use of 3D devices, tougher requirements are now imposed on device inspection both during original manufacture and at their subsequent processing onto printed circuit boards. More complicated and de
Technical Library | 2021-08-11 01:00:37.0
Conformal coatings and potting materials continue to create issues for the electronics industry. This webinar will dig deeper into the failure modes of these materials, specifically issues with Coefficient of Thermal Expansion (CTE), delamination, cracking, de-wetting, pinholes/bubbles and orange peel issues with conformal coatings and what mitigation techniques are available. Similarly, this webinar will look at the failure modes of potting materials, (e.g Glass Transition Temperature (Tg), PCB warpage, the effects of improper curing and potential methods for correcting these situations.
Technical Library | 2013-03-27 23:43:40.0
Vapor phase, once cast to the annals’ of history is making a comeback. Why? Reflow technology is well developed and has served the industry for many years, it is simple and it is consistent. All points are true – when dealing with the centre section of the bell curve. Today’s PCB manufacturers are faced with many designs which no longer fall into that polite category but rather test the process engineering groups with heavier and larger panels, large ground planes located in tricky places, component mass densities which are poorly distributed, ever changing Pb Free alloys and higher process temperatures. All the time the costs for the panels increase, availability of “process trial” boards diminishes and yields are expected to be extremely high with zero scrap rates. The final process in the assembly line has the capacity to secure all the value of the assembly or destroy it. If a panel is poorly soldered due to poor Oven setup or incorrect programming of the profile the recovery of the panel is at best expensive, at worst a loss. For these challenges people are turning to Vapor Phase.
Technical Library | 2013-04-25 11:42:01.0
Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2013-10-10 16:28:21.0
In the past 15 years, stretchable electronic circuits have emerged as a new technology in the domain of assembly, interconnections, and sensor circuit technologies. In the meantime, a wide variety of processes using many different materials have been explored in this new field. In the current contribution, we present an approach inspired by conventional rigid and flexible printed circuit board (PCB) technology.
Technical Library | 2019-09-19 00:28:48.0
The symbiotic relationship between solder masks and selective finishes is not new. The soldermask application is one of the key considerations to ensure a successful application of a selective finish. The selective finish is the final chemical step of the PCB manufacturing process, this is when the panels are at their most valuable and are unfortunately not re-workable. Imperfections are not tolerated, even if they are wholly cosmetic. Quality issues often manifest themselves in the form of a 'ping pong' conversation between the fabricators, the soldermask suppliers and the selective finish suppliers. Without tangible evidence these discussions are difficult to resolve and the selective finish process is usually regarded as responsible. This paper will focus on the chemical characteristics and use them to predict or identify potential issues before they occur rather than specifically name 'critical' soldermasks. It is also the intention of this paper to address the potential of a soldermask to react to common yield hiking practices like UV bumping and oven curing. It is hoped that this awareness will help fabricators to ensure maximum yields by asking the right questions. 'Critical’ soldermasks impact all selective finishes. In this paper, practical experience using immersion tin will be used to highlight the relationship between 'critical' soldermasks and some of the issues seen in the field. The paper will include a novel approach to identify re-deposited volatiles after the reflow.
Technical Library | 2020-03-26 14:55:29.0
This paper introduces line confocal technology that was recently developed to characterize 3D features of various surface and material types at sub-micron resolution. It enables automatic microtopographic 3D imaging of challenging objects that are difficult or impossible to scan with traditional methods, such as machine vision or laser triangulation.Examples of well-suited applications for line confocal technology include glossy, mirror-like, transparent and multi-layered surfaces made of metals (connector pins, conductor traces, solder bumps etc.), polymers (adhesives, enclosures, coatings, etc.), ceramics (components, substrates, etc.) and glass (display panels, etc.). Line confocal sensors operate at high speed and can be used to scan fast-moving surfaces in real-time as well as stationary product samples in the laboratory. The operational principle of the line confocal method and its strengths and limitations are discussed.Three metrology applications for the technology in electronics product manufacturing are examined: 1. 3D imaging of etched PCBs for micro-etched copper surface roughness and cross-sectional profile and width of etched traces/pads. 2. Thickness, width and surface roughness measurement of conductive ink features and substrates in printed electronics applications. 3. 3D imaging of adhesive dots and lines for shape, dimensions and volume in PCB and product assembly applications.
Technical Library | 2017-05-04 17:35:01.0
Most of today's printed circuit board base materials are anisotropic and it is not possible to use a simple method to measure thermal conductivity along the different axis, especially when a good accuracy is expected. Few base material suppliers' datasheet show X, Y and Z thermal conductivities. In most cases, a single value is given, moreover determined with a generic methodology, and not necessarily adapted to the reality of glass-reinforced composites with a strong anisotropy.After reminding of the fundamentals in thermal science, this paper gives an overview of the state-of the art in terms of thermal conductivity measurement on PCB base materials, and some typical values. It finally proposes an innovative method called transient fin method, and associated test sample, to perform reliable and consistent in plane thermal conductivity measurement on anisotropic PCB base materials.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2021-06-07 19:06:32.0
The technological growth of the last decades has brought many improvements in daily life, but also concerns on how to deal with electronic waste. Electrical and electronic equipment waste is the fastest-growing rate in the industrialized world. One of the elements of electronic equipment is the printed circuit board (PCB) and almost every electronic equipment has a PCB inside it. While waste PCB (WPCB) recycling may result in the recovery of potentially precious materials and the reuse of some components, it is a challenging task because its composition diversity requires a cautious pre-processing stage to achieve optimal recycling outcomes. Our research focused on proposing a method to evaluate the economic feasibility of recycling integrated circuits (ICs) from WPCB. The proposed method can help decide whether to dismantle a separate WPCB before the physical or mechanical recycling process and consists of estimating the IC area from a WPCB, calculating the IC's weight using surface density, and estimating how much metal can be recovered by recycling those ICs. To estimate the IC area in a WPCB, we used a state-of-the-art object detection deep learning model (YOLO) and the PCB DSLR image dataset to detect the WPCB's ICs. Regarding IC detection, the best result was obtained with the partitioned analysis of each image through a sliding window, thus creating new images of smaller dimensions, reaching 86.77% mAP. As a final result, we estimate that the Deep PCB Dataset has a total of 1079.18 g of ICs, from which it would be possible to recover at least 909.94 g of metals and silicon elements from all WPCBs' ICs. Since there is a high variability in the compositions of WPCBs, it is possible to calculate the gross income for each WPCB and use it as a decision criterion for the type of pre-processing.
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