Technical Library: pcb military (Page 1 of 1)

21st Century PCB FAB Factory Design Which Eliminates Regional Cost Advantages

Technical Library | 2017-11-01 17:06:38.0

Over fifteen years has passed since North America and Europe ceased being the center of worldwide PCB fabrication, and were supplanted by a Far East market with low cost labor, more relaxed environmental requirements, and strong government support. In just a few short years, the superior cost advantages of this new dynamic put volume PCB production in the West out of business, aside for the military and specialty technology applications contained in the few shops that continue to exist today.Recently, however, the conditions which created the current equilibrium appear to be shifting again. In this new dynamic, automation, innovative green wastewater technologies, and next generation process equipment innovations have combined to make new factories capable of achieving rapid ROI for PCB fabrication almost anywhere. This paper means to illustrate this new dynamic, and provide case study examples from the new greenfield installation at the company captive facility in New Hampshire.

Whelen Engineering

PTH Core-to-Core Interconnect Using Sintered Conductive Pastes

Technical Library | 2013-03-07 18:25:36.0

The market for high-layer-count printed circuit boards (PCB) containing blind and buried vias was once relatively small, and focused on specialized applications in the military and high end computing. The demand for these types of PCBs today is being driven by an increasing number of commercial applications in the telecommunications and semiconductor test market segments. These applications typically require high-aspect-ratio plated-through-holes (PTHs) and blind and buried vias in order to meet the applications interconnect density requirements. Blind and buried vias and high aspect ratio PTHs continue to present manufacturing challenges and frequently are the limiting features to achieving high fabrication yield... First published in the 2012 IPC APEX EXPO technical conference proceedings

Ormet Circuits, Inc.

Review of Interconnect Stress Testing Protocols and Their Effectiveness in Screening Microvias

Technical Library | 2016-11-30 15:53:15.0

The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.

Raytheon

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