Technical Library | 2012-12-27 14:35:29.0
Printed Electronics is generally defined as the patterning of electronic materials, in solution form, onto flexible substrates, omitting any use of the photolithography, etching, and plating steps commonly found within the Printed Circuit Board (PCB) industry. The origins of printed electronics go back to the 1960s, and close variants of several original applications and market segments remain active today. Through the 1980s and 1990s Printed Electronic applications based on Membrane Touch Switch and Electroluminescent lighting technologies became common, and the screen printed electronic materials used then have formed the building blocks for many of the current and emerging technologies and applications... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2014-05-01 15:14:12.0
Bilayer graphene has been a subject of intense study in recent years. The interlayer registry between the layers can have dramatic effects on the electronic properties: for example, in the presence of a perpendicular electric field, a band gap appears in the electronic spectrum of so-called Bernal-stacked graphene. This band gap is intimately tied to a structural spontaneous symmetry breaking in bilayer graphene, where one of the graphene layers shifts by an atomic spacing with respect to the other. This shift can happen in multiple directions, resulting in multiple stacking domains with soliton-like structural boundaries between them
Technical Library | 2014-12-11 18:00:09.0
The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Wire bonded packages using conventional copper lead frame have been used in industry for quite some time. However, the demand for consumer electronics is driving the need for flip chip interconnects as these packages shorten the signals, reduce inductance and improve functionality as compared to the wire bonded packages. The flip chip packages have solder bumps as interconnects instead of wire bonds and typically use an interposer or organic substrate instead of a metal lead frame (...) The paper provides a general overview of typical defects and failure modes seen in package assembly and reviews the efforts needed to understand new failure modes during package assembly. The root cause evaluations and lessons learned as the factory transitioned to thin form factor packages are shared
Technical Library | 2015-04-02 20:12:58.0
The demands on volume delivery and positioning accuracy for solder paste deposits are increasing as the size and complexity of circuits continue to develop in the electronics industry. According to the iNEMI 2013 placement accuracy for these kinds of components will reach 6 sigma placement accuracy in X and Y of 30 um by 2023.This study attempts to understand the dependencies on piezo actuation pulse profile on jetting deposit quality, especially focused on positioning, satellites and shape. The correlation of deposit diameter and positioning deviation as a function of piezo actuation profile shows that positioning error for deposits increase almost monotonically with decreasing droplet volume irrespective of the piezo-actuation profile. The trends for shape and satellite levels are not as clear and demand further study.
Technical Library | 2012-11-12 14:06:48.0
With consumers constantly looking for lower prices on their technology products and manufacturers trying to squeak out higher margins from their production lines, the need for process control and lower overhead costs have become even more important. One sector that is often overlooked is the hand soldering area of the factory. Many factories have been struggling with antiquated soldering systems for years. In some cases they are trying to make their investment in stations last much longer than they were designed for, or they are falsely trying to recoup their original investment ‐ all at the cost of higher operating expenses or even worse, reduced operator thru‐put.
Technical Library | 2018-10-24 18:04:12.0
Polymer Thick Film (PTF)-based printed electronics (aka Printed Electronics) has improved in durability over the last few decades and is now a proven alternative to copper circuitry in many applications once thought beyond the capability of PTF circuitry. This paper describes peak performance and areas for future improvement.State-of-the-art PTF circuitry performance includes the ability to withstand sharp crease tests, 85C/85%RH damp heat 5VDC bias aging (silver migration), auto seat durability cycling, SMT mandrel flexing, and others. The IPC/SGIA subcommittee for Standards Tests development has adopted several ASTM test methods for PTF circuitry and is actively developing needed improvements or additions. These standards are described herein. Advantages of PTF circuitry over copper include: varied conductive material compositions, lower cost and lower environmental impact. Necessary improvements include: robust integration of chip and power, higher conductivity, and fine line multi-layer patterning.
Technical Library | 2020-02-19 23:12:55.0
Silver nanowires (Ag NWs) possess excellent optoelectronic properties, which have led to many technology-focused applications of transparent and flexible electronics. Many of these applications require patterning of Ag NWs into desired shapes, for which mask-based and printing-based techniques have been developed and widely used. However, there are still several limitations associated to these techniques. These limitations, such as complicated patterning procedures, limited patterning area, and compromised optical transparency, hamper the efficient fabrication of high-performance Ag NW patterns. Here, we propose a coat-and-print approach for effectively patterning Ag NWs.
Integrated Microwave Packaging Antennas and Circuits Technology (IMPACT) Lab
Technical Library | 2022-12-05 16:28:06.0
The work evaluates the impact of latent heat (LH) absorbed or released by a solder alloy during melting or solidification, respectively, on changes of dimensions of materials surrounding of the solder alloy. Our sample comprises a small printed circuit board (PCB) with a blind via filled with lead-free alloy SAC305. Differential scanning calorimetry (DSC) was employed to obtain the amount of LH per mass and a thermomechanical analyzer was used to measure the thermally induced deformation. A plateau during melting and a peak during solidification were detected during the course of dimension change. The peak height reached 1.6 μm in the place of the heat source and 0.3 μm in the distance of 3 mm from the source. The data measured during solidification was compared to a numerical model based on the finite element method. An excellent quantitative agreement was observed which confirms that the transient expansion of PCB during cooling can be explained by the release of LH from the solder alloy during solidification. Our results have important implications for the design of PCB assemblies where the contribution of recalescence to thermal stress can lead to solder joint failure.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
Technical Library | 2023-12-18 21:07:29.0
Selective soldering utilises a nozzle to apply solder to components on the underside of printed circuit boards (PCBs). This nozzle can be moved to either perform dips (depositing solder to a single component) or draws (applying solder to several components in a single movement). The selective soldering methodology thereby allows the process to be tailored to specific joints and allows multiple nozzle types to be used if required on the circuit board. Nozzles can vary by size (internal diameter) and shape (making them suitable for different process types). This is all dictated by board design and process requirements. Selection of the nozzle type is dependent upon the product to be soldered and the desired cycle time. Examples of different nozzle types are shown here. Hand-load selective systems must be programmed with the parameters for multiple solder joints. However, many in-line systems are designed to be modular. This modularity allows for multiple solder stations with different conditions/nozzles to achieve low cycle times. Figure 1 shows the two distinct types of selective soldering systems offered by Pillarhouse International Ltd.
