Technical Library | 2017-03-02 18:13:05.0
The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS) transistors has become a major concern as the power consumption of electronic integrated circuits (ICs) steadily increases with technology scaling. Nano-Electro-Mechanical (NEM) relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays) have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.
Technical Library | 2019-11-12 02:09:22.0
Thermal shock test chamber can be used for testing the chemical change or physical damage on composite materials caused by the thermal expansion and contraction of the sample in the shortest time,which is subjected to extremely and continuous high and low temperature environment.so how to check the temperature recovery time of this chamber? Normally we take following steps to inspect the temepratuire recovering time: 1.Install the temperature sensor at the specified position, and adjust the temperature controller of hot zone and cold zone to the required nominal temperature respectively. 2.The temperature increases and reduces respectively,30min after temperature in two zones reach stable status,record temperature value of the measuring point,pls set the temperature value of two zones to be required nominal temperature. 3.The temperature shock test chamber automatically places the inspected load into theh ot zone,select the corresponding retention time according to regulated standard. 4.Set the transfer time,then the inspection load is transferred from hot zone to cold zone, and the temperature of the measuring point is observed and recorded, and then the reverse conversion of the load from cold zone to hot zone is carried out according to the same method, and the temperature of the measuring point is observed and recorded. www.climatechambers.com
Technical Library | 2020-08-19 19:13:00.0
Commercially available health monitors rely on rigid electronic housing coupled with aggressive adhesives and conductive gels, causing discomfort and inducing skin damage. Also, research-level skin-wearable devices, while excelling in some aspects, fall short as concept-only presentations due to the fundamental challenges of active wireless communication and integration as a single device platform. Here, an all-in-one, wireless, stretchable hybrid electronics with key capabilities for real-time physiological monitoring, automatic detection of signal abnormality via deep-learning, and a long-range wireless connectivity (up to 15 m) is introduced. The strategic integration of thin-film electronic layers with hyperelastic elastomers allows the overall device to adhere and deform naturally with the human body while maintaining the functionalities of the on-board electronics. The stretchable electrodes with optimized structures for intimate skin contact are capable of generating clinical-grade electrocardiograms and accurate analysis of heart and respiratory rates while the motion sensor assesses physical activities. Implementation of convolutional neural networks for real-time physiological classifications demonstrates the feasibility of multifaceted analysis with a high clinical relevance. Finally, in vivo demonstrations with animals and human subjects in various scenarios reveal the versatility of the device as both a health monitor and a viable research tool.
Technical Library | 2014-07-31 16:36:59.0
Metal whiskers often grow across leads of electric equipment and electronic package causing current leakage or short circuits and raising significant reliability issues. The nature of metal whiskers remains a mystery after several decades of research. Here, the existence of metal whiskers is attributed to the energy gain due to electrostatic polarization of metal filaments in the electric field. The field is induced by surface imperfections: contaminations, oxide states, grain boundaries, etc. A proposed theory provides closed form expressions and quantitative estimates for the whisker nucleation and growth rates, explains the range of whisker parameters and effects of external biasing, and predicts statistical distribution of their lengths.
Technical Library | 2021-11-03 17:05:39.0
Additively printed circuits provide advantages in reduced waste, rapid prototyping, and versatile flexible substrate choices relative to conventional circuit printing. Copper (Cu) based inks along with intense pulsed light (IPL) sintering can be used in additive circuit printing. However, IPL sintered Cu typically suffer from poor solderability due to high roughness and porosity. To address this, hybrid Cu ink which consists of Cu precursor/nanoparticle was formulated to seed Cu species and fill voids in the sintered structure. Nickel (Ni) electroplating was utilized to further improve surface solderability. Simulations were performed at various electroplating conditions and Cu cathode surface roughness using the multi-physics finite element method. By utilizing a mask during IPL sintering, conductivity was induced in exposed regions; this was utilized to achieve selective Ni-electroplating. Surface morphology and cross section analysis of the electrodes were observed through scanning electron microscopy and a 3D optical profilometer. Energy dispersive X-ray spectroscopy analysis was conducted to investigate changes in surface compositions. ASTM D3359 adhesion testing was performed to examine the adhesion between the electrode and substrate. Solder-electrode shear tests were investigated with a tensile tester to observe the shear strength between solder and electrodes. By utilizing Cu precursors and novel multifaceted approach of IPL sintering, a robust and solderable Ni electroplated conductive Cu printed electrode was achieved.
Technical Library | 2019-11-17 22:46:45.0
Overview of walk-in temperature and humidity chamber: It also belongs to environmental test equipment, it tests whether the product can resist high temperature, low temperature, humidity, or the physical and chemical changes produced under extreme conditions, the walk-in temperature and humidity chamber volume is large, the product is placed, or a large object can be placed, such as automobile, new energy, television and liquid crystal screen, etc. How to do the routine maintenance of the walk-in temperature and humidity chamber: 1. The wet gauze basically, if there is no special case, s/b usually changed once in 3 months 2. The water channel shall be regularly cleaned, including water cup, water tank, etc., so as to prevent the water from being blocked,affect the humidity test. 3. It is forbidden to test the flammable and explosive products inside working room. 4. Clean the chamber on a regular basis 2. How to operate walk-in temperature and humidity chamber: The operation method is same as standard temperature humidity test chamber,the controller is 7-inch LCD programmable color screen, you only need to setthe temperature point---test time--how many cycles need to be tested, This can be done automatically, and the machine will stop automatically when it is complete. If there is any problem during the operation, the corresponding problem point will be displayed on the machine control screen. Walk-in temperature and humidity chamber is a must equipment for reliability test of Automobile,Aerospace,Electronic parts,etc,the operation and maintenance are easy,it is teh tear down mahcine,Climatest engineers will be dispatched to do on-site support,for instance,we will finish commissioning,train customers how to operate,maintain,welcome to follow our company facebook page:https://www.facebook.com/Climatechambers
Technical Library | 2021-06-07 19:06:32.0
The technological growth of the last decades has brought many improvements in daily life, but also concerns on how to deal with electronic waste. Electrical and electronic equipment waste is the fastest-growing rate in the industrialized world. One of the elements of electronic equipment is the printed circuit board (PCB) and almost every electronic equipment has a PCB inside it. While waste PCB (WPCB) recycling may result in the recovery of potentially precious materials and the reuse of some components, it is a challenging task because its composition diversity requires a cautious pre-processing stage to achieve optimal recycling outcomes. Our research focused on proposing a method to evaluate the economic feasibility of recycling integrated circuits (ICs) from WPCB. The proposed method can help decide whether to dismantle a separate WPCB before the physical or mechanical recycling process and consists of estimating the IC area from a WPCB, calculating the IC's weight using surface density, and estimating how much metal can be recovered by recycling those ICs. To estimate the IC area in a WPCB, we used a state-of-the-art object detection deep learning model (YOLO) and the PCB DSLR image dataset to detect the WPCB's ICs. Regarding IC detection, the best result was obtained with the partitioned analysis of each image through a sliding window, thus creating new images of smaller dimensions, reaching 86.77% mAP. As a final result, we estimate that the Deep PCB Dataset has a total of 1079.18 g of ICs, from which it would be possible to recover at least 909.94 g of metals and silicon elements from all WPCBs' ICs. Since there is a high variability in the compositions of WPCBs, it is possible to calculate the gross income for each WPCB and use it as a decision criterion for the type of pre-processing.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
Technical Library | 2019-04-08 23:21:29.0
Climatest Symor® adopts molecular sieve to dry air, the whole system is controlled by microcomputer, when humidity is high, It will start to absorb moisture,when the humidity reach the pre-set value, it will stop absorbing, and then discharge the water to outside the cabinet by heating,again and again by automatic control. The most effective and environment-friendly moisture-absorbing desiccant is molecular sieve, molecular sieve is the microporous crystal material synthesized by silicon and aluminium oxide. In order to keep the crystal net discharge to be zero, atoms with cations are located in the crystal structure.and the cation used in these synthetic crystals is usually sodium. At present, there are two kinds of molecular sieves widely used in the dry box industry: Class A and Class X. Molecular sieves are synthesized, shaped and activated under strictly controlled production processes. The whole controlled sythesis process can ensure consistency of the three-dimensional pore size. 3A molecular sieve pore size is 3 angstroms, 4A molecular sieve pore size is 4 angstroms; 13X molecular sieve pore size is 8.5 angstroms. The working principle of molecular sieve: Molecular sieves adsorb molecules onto the crystal surface by physical attraction force. Since 95% surface area of the molecular sieve is within aperture,it needs to screen the adjacent molecules by different size. Only small size molecules can enter into the inner adsorption surface of the molecular sieve through the crystal aperture. This selective adsorption phenomenon is called molecular sieve effect. The molecular sieve adsorption capacity and charge density (polarity) are further related to the adsorbed molecules. The molecular sieves can further distinguish which of the mixed molecules can be adsorbed and determine to what extent the charge density can allow the molecules to be adsorbed onto the crystal. Water molecules are particularly small (2.6 angstroms), that belong to highly polar molecules (very strong positive and negative electron density), and are easily adsorbed by molecular sieves, even under very low moisture condition,once the water molecules are adsorbed,they will be firmly fixed on the crystal. The environment-friendly moisture absorption device is equipped with molecular sieve. When it’s absorbing, the memory alloy controller is in tensile state, and the spring is in contractive state,which just make the valve contact the outer baffle, this insulates the outside air from inside dry box air to achieve dehumidification purpose; and after molecular sieve absorbed moisture inside dry box and become saturated, the program will automatically control the memory alloy device to shrink it so that the valve reaches the inner baffle position. Meanwhile, due to the shrinkage of the memory alloy, the spring is stretched and the valve is pulled out of the outer baffle,so that the moisture in molecular sieve will be discharged into the outside. after the dehumidifying process finished, the program automatically control and reset the memory alloy and spring,to restart absorbing status.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
