Technical Library | 2007-06-27 15:43:06.0
Traditionally most flip chips were designed with large bumps on a coarse pitch. However, as the trend towards smaller, more compact assemblies continues the sizes of semiconductor packages are forced to stay in line. New designs are incorporating smaller bump diameters on increasingly aggressive pitches, and in many cases decreasing the total IO count. With fewer and smaller bumps to distribute the load of the placement force it is becoming increasingly vital for equipment manufacturers to meet the challenge in offering low force placement solutions. One such solution will be presented in the following discussion. Also presented will be ways to minimize the initial impact spike that flip chips experience upon placement.
Technical Library | 2007-08-09 12:23:10.0
Recent developments in No Flow-Fluxing Underfill (NFFUF) products have demonstrated their utility to enhance the reliability of flip chip assemblies with reduced processing steps over conventional capillary flow methods. This basic work considered processing conditions such as dispensed volume and placement force, speed and dwell time. Further evaluations of these new products on a variety of flip chip assembly configurations manufactured by various processes have been undertaken to provide further evidence of their suitability and potential in high volume electronic manufacturing. This paper summarizes the recent evaluations and discusses new studies of additional assembly configurations, which include higher input/output (l/O) counts up to full arrays in excess of 1200 l/Os.
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