Technical Library | 2024-08-29 18:30:46.0
The mechanical experience of consumption (i.e., feel, softness, and texture) of many foods is intrinsic to their enjoyable consumption, one example being the habit of twisting a sandwich cookie to reveal the cream. Scientifically, sandwich cookies present a paradigmatic model of parallel plate rheometry in which a fluid sample, the cream, is held between two parallel plates, the wafers. When the wafers are counterrotated, the cream deforms, flows, and ultimately fractures, leading to separation of the cookie into two pieces. We introduce Oreology (/Oriːˈɒl@dʒi/), from the Nabisco Oreo for "cookie" and the Greek rheo logia for "flow study," as the study of the flow and fracture of sandwich cookies. Using a laboratory rheometer, we measure failure mechanics of the eponymous Oreo's "creme" and probe the influence of rotation rate, amount of creme, and flavor on the stress–strain curve and postmortem creme distribution. The results typically show adhesive failure, in which nearly all (95%) creme remains on one wafer after failure, and we ascribe this to the production process, as we confirm that the creme-heavy side is uniformly oriented within most of the boxes of Oreos. However, cookies in boxes stored under potentially adverse conditions (higher temperature and humidity) show cohesive failure resulting in the creme dividing between wafer halves after failure. Failure mechanics further classify the creme texture as "mushy." Finally, we introduce and validate the design of an open-source, three-dimensionally printed Oreometer powered by rubber bands and coins for encouraging higher precision home studies to contribute new discoveries to this incipient field of study
Technical Library | 2013-01-31 18:43:15.0
There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices, the emergence of lead-free processing, and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide. First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2020-03-12 13:10:35.0
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs.
Technical Library | 2015-06-04 19:10:47.0
Integrators and designers of high-reliability systems exert little or no control over component-level plating processes that affect the propensity for tin whiskering. Challenges of how to assure long-term reliability, while continuing to use COTS parts plated with pure tin, continue to arise. An integrated, quantitative, standardized methodology is proposed whereby mitigation levels can be selected that are appropriate for specific applications of pure tin for given end-uses. A system of hardware end-use classification is proposed, together with recommended appropriate risk mitigation approaches. An updated version of the application-specific risk assessment algorithm is presented together with recommended thresholds for acceptability within the context of the hardware classifications.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2013-01-17 15:34:33.0
The use of an electroless nickel, immersion gold (ENIG) surface finish comes with the inherent potential risk of Black Pad failures that can cause fracture embrittlement at the interface between the solder and the metal pad. As yet, there is no conclusive agreed solution to effectively eliminate Black Pad failures. The case studies presented are intended to add to the understanding of the Black Pad failure mechanism and to identify both the plating and the subsequent assembly processes and conditions that can help to prevent the likelihood of Black Pad occurring.
Technical Library | 2013-10-31 17:36:41.0
Multilayer printed circuit boards (PCBs) that utilize high performance materials are inherently far more challenging for a fabricator to build, due to significant material property differences over standard epoxy glass FR4. These unique material characteristics often require higher processing temperatures, special surface treatments (to aid in hole and surface plating), they possess different expansion properties, making layer-to-layer registration more difficult to control, and require many other unique considerations.
Technical Library | 2015-12-23 16:57:27.0
The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects, the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly, there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.
Technical Library | 2021-12-21 23:15:44.0
High Density Interconnect (HDI) technologies are being used widely in Asia and Europe in consumer electronics for portable wireless communication and computing, digital imaging, and chip packaging. Although North America lags behind in developing process capability for this technology, HDI will become a significant business segment for North America. For this to happen, the printed circuit board shops will have to become process capable in fabricating fine lines and spaces, and also be capable in forming and plating microvias.
Technical Library | 2019-11-07 08:59:14.0
Inductors realized with high permeable MnZn ferrite require, unlike iron-powder cores with an inherent dis-tributed gap, a discrete air gap in the magnetic circuit to prevent saturation of the core material and/or tune the inductance value. This large discrete gap can be divided into several partial gaps in order to reduce the air gap stray field and consequently the proximity losses in the winding. The multi-gap core, realized by stacking several thin ferrite plates and inserting a non-magnetic spacer material between the plates, however, exhibits a substan-tial increase in core losses which cannot be explained from the intrinsic properties of the ferrite. In this paper, a comprehensive overview of the scientific literature regarding machining induced core losses in ferrite, dating back to the early 1970s, is provided which suggests that the observed excess core losses could be attributed to a deterioration of ferrite properties in the surface layer of the plates caused by mechanical stress exerted during machining.
