Technical Library | 2023-05-02 19:06:43.0
As 0402 has become a common package for printed circuit board (PCB) assembly, research and development on mounting 0201 components is emerging as an important topic in the field of surface mount technology for PWB miniaturization. In this study, a test vehicle for 0201 packages was designed to investigate board design and assembly issues. Design of Experiment (DOE) was utilized, using the test vehicle, to explore the influence of key parameters in pad design, printing, pick-andplace, and reflow on the assembly process. These key parameters include printing parameters, mounting height or placement pressure, reflow ramping rate, soak time and peak temperature. The pad designs consist of rectangular pad shape, round pad shape and home-based pad shape. For each pad design, several different aperture openings on the stencil were included. The performance parameters from this experiment include solder paste height, solder paste volume and the number of post-reflow defects. By analyzing the DOE results, optimized pad designs and assembly process parameters were determined.
Technical Library | 2012-10-25 16:34:02.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper will examine stencil technologies (including Laser and Electroform), Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings), and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.
Technical Library | 2019-03-13 15:19:55.0
It is well documented that Nano coatings on SMT stencils offer many benefits to those assembling PWBs. With reduced standard deviation and improved transfer efficiency nano coatings can provide, there is also a cost. As PWB assemblers work to justify the return on investment, one key question continues to arise. What is the durability or life of these coatings and what can be done in the print process to maximize the life of the coatings?This paper addresses durability of the coatings in relation to the number of print cycles and underside wipe cycles applied as well as materials used on the underside wipe process. Different parameters will be applied and data will be collected. The results of this study will be summarized to help those using or considering the use of these nano coatings to improve their print process and suggestions will be given to maximize the life of the coatings.
Technical Library | 2011-10-20 22:03:30.0
Results of FEM modelling of thermal stress analysis in printed circuit boards are given in the article. It is shown that thermal stress alone is not solely caused by differences in coefficients of thermal expansion of individual layers. The emergence of thermal stress is subject to both the layered structure of the wall and given boundary conditions, as well as the existence of a temperature gradient in the direction normal to the surface of the wall. A practical application focuses on the issue of recycling of PCB with the effort to achieve separation of layers due to thermal stress. Role modelling of thermal stress in this area lies in predicting the possibility of separation, depending on the type of thermal stress and material parameters.
Technical Library | 2018-11-06 12:42:25.0
Solder paste is a homogeneous, stable suspension of solder powder particles suspended in a flux binder, and is one of the most important process materials today in surface mount technology (SMT). By varying the solder particle size, distribution and shape, as well as the other constituent materials, the rheology and printing performance of solder pastes can be controlled. Paste flow behavior is very important in defining the printing performance of any paste.The purpose of this paper is to study the rheological behavior of SAC (Sn-Ag-Cu) solder paste used for surface mount applications in the electronic industry. The reason why the rheological tests are presented in this paper are two critical sub-processes: aperture filling and paste withdraw. In this paper, we report on the investigation of the rheological profiles, the serrated cone-to-plate system was found as effective in parameter minimizing the wall-slip effect
Technical Library | 2016-10-27 16:24:23.0
Press-fit technology is a proven and widely used and accepted interconnection method for joining electronics assemblies. Printed Circuit Board Assembly Systems and typical functional subassemblies are connected through press-fit connectors. The Press-Fit Compliant Pin is a proven interconnect termination to reliably provide electrical and mechanical connections from a Printed Circuit Board to an Electrical Connector. Electrical Connectors are then interconnected together providing board to board electrical and mechanical inter-connection. Press-Fit Compliant Pins are housed within Connectors and used on Backplanes, Mid-planes and Daughter Card Printed Circuit Board Assemblies. High reliability OEM (Original Equipment Manufacturer) computer designs continue to use press-fit connections to overcome challenges associated with soldering, rework, thermal cycles, installation and repair. This paper investigates the technical roadmap for press fit technology, putting special attention to main characteristics such, placement and insertion, inspection, repair, pin design trends, challenges and solutions. Critical process control parameters within an assembly manufacturing are highlighted.
Technical Library | 2018-10-18 15:41:45.0
One specific market space of interest to emerging printed electronics is In Mold Label (IML) technology. IML is used in many consumer products and white good applications. When combined with electronics, the In Mold Electronics (IME) adds compelling new product functionality. Many of these products have multi-dimensional features and therefore require thermoforming processes in order to prepare the labels before they are in-molded. While thermoforming is not a novel technique for IML, the addition of printed electronic functional traces is not well documented. There is little or no published work on printed circuit performance and design interactions in the thermoforming process that could inform improved IME product designs. A general full factorial Design of Experiments (DOE) was used to analyze the electrical performance of the conductive silver ink trace/polycarbonate substrate system. Variables of interest include trace width, height of draw, and radii of both top and bottom curvatures in the draw area. Thermoforming tooling inserts were fabricated for eight treatment combinations of these variables. Each sample has one control and two formed strips. Electrical measurements were taken of the printed traces on the polymer sheets pre- and post- forming with a custom fixture to evaluate the effect on resistance. The design parameters found to be significant were draw height and bottom radius, with increased draw and smaller bottom curvature radii both contributing to the circuits’ resistance degradation. Over the ranges evaluated, the top curvature radii had no effect on circuit resistance. Interactions were present, demonstrating that circuit and thermoforming design parameters need to be studied as a system. While significant insight impacting product development was captured further work will be executed to evaluate different ink and substrate material sets, process variables, and their role in IME.
Technical Library | 2021-09-01 15:31:39.0
The long-standing trend in the electronics industry has been the miniaturization of electronic components. It is projected that this trend will continue as Original Equipment Manufacturers (OEMs) and Electronic Manufacturing Service (EMS) providers strive to reduce "real estate" on printed circuit boards. Typically, the miniaturization of components can be achieved by integration or size reduction. At present, size reduction is considered to be more cost effective and flexible than integration. Passive components, which are used in limiting current, terminating transmission lines and de-coupling switching noise, are the primary focus in size reduction due to their variety of uses.
Technical Library | 2018-03-28 14:54:36.0
Six decades of legacy experience makes the specification and production of screens and masks to produce repeatable precision results mostly an exercise in matching engineering needs with known ink and substrate performance to specify screen and stencil characteristics. New types of functional and electronic devices, flex circuits and medical sensors, industrial printing, ever finer circuit pitch, downstream additive manufacturing processes coupled with new substrates and inks that are not optimized for the rheological, mechanical and chemical characteristics for the screen printing process are becoming a customer driven norm. Many of these materials do not work within legacy screen making, curing or press set-up parameters. Many new materials and end uses require new screen specifications.This case study presents a DOE based method to pre-test new materials to categorize ink and substrate rheology, compatibility and printed feature requirement to allow more accurate screen recipes and on-press setting expectations before the project enters the production environment where time and materials are most costly and on-press adjustment methods may be constrained by locked, documented or regulatory processes, equipment limitations and employee experience.
Technical Library | 2019-09-11 23:33:04.0
There are numerous techniques to singulate printed circuit boards after assembly including break-out, routing, wheel cutting and now laser cutting. Lasers have several desirable advantages such as very narrow kerf widths as well as virtually no dust, no mechanical stress, visual pattern recognition and fast set-up changes. The very narrow kerf width resulting from laser ablation and the very tight tolerance of the cutting path placement allows for more usable space on the panel. However, the energy used in the laser cutting process can also create unwanted products on the cut walls as a result of the direct laser ablation. The question raised often is: What are these products, and how far can the creation of such products be mitigated through variation of the laser cutting process, laser parameters and material handling? This paper discusses the type and quantity of the products found on sidewalls of laser depaneled circuit boards and it quantifies the results through measurements of breakdown voltage, as well as electrical impedance. Further this paper discusses mitigation strategies to prevent or limit the amount of change in surface quality as a result of the laser cutting process. Depending on the final application of the circuit board it may prompt a need for proper specification of the expected results in terms of cut surface quality. This in turn will impact the placement of runs and components during layout. It will assist designers and engineers in defining these parameters sufficiently in order to have a predictable quality of the circuit boards after depaneling.
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